[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [XEN v2 04/12] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32
- To: Julien Grall <julien@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Ayan Kumar Halder <ayankuma@xxxxxxx>
- Date: Mon, 7 Nov 2022 11:33:15 +0000
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2HEMvp3MyZ9J4dHmLMpIh6FR/Xf+YNy3jfWaVMUQg8E=; b=g6jxeqAFxzSvkGiIL7suwYNyp7KHAH/4IXCxEEPMYOYSENwsvfupb/O1IPEIIGIOUVIzqNEgwtIf5R0/r+Tu/Np0OXY+YvOwUihjkKGLyXzohYvzL5HyyUlsjoBdxBZwGTeBgN+3Bnbq1Kb986b8cvNQbMz0xXVJNhFb1DVfLdT0Gkmb9alMFbA9uPWeV3U7I25cD6ouCo7asQP//24ciFsqjZ5/ONMsNk1hPiKrOad+wR5uSBxcQz7oe2/rEB/6cB4B87P6xMlkISYbfcmpD0cwQp6xaPyq2Y5/k1o/yP03W5SPoaHRue1NO+UpeUPptuqzNECWAPoLvQhetF48qQ==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WohRqy3TWCMsecD3e+SS36ObHev+PYCWtYMX2lDC9fs44dB2BkMrgVLzEVtzDckFBN8S0FP0gyA/U6fgxw7Ieg9pYVIbIryZPKoMweoAK/aIx0+o5YBnfaVOeym4s9xmIj/pxuwtk7XIhhiiXzTWpCUgAKMsxJEZUgGZlgToTfqInSRDhcwc87dv3yW1px5/Edm7zq6g6M0m+jMLOWiU6vp3/zn4GdBcnruoUjvFW28L9nfZmHgxVZnYdzsyXSMjupfWLINPciof6ZQghAWYAgvB4WP+60/w/9sJqcnIAYVw6F+vA+UE+vB6sB+FvNZbGyI8nUDlBfkKMXjuVPf/Eg==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
- Cc: sstabellini@xxxxxxxxxx, stefanos@xxxxxxxxxx, Volodymyr_Babchuk@xxxxxxxx, bertrand.marquis@xxxxxxx, burzalodowa@xxxxxxxxx
- Delivery-date: Mon, 07 Nov 2022 11:33:42 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 06/11/2022 18:04, Julien Grall wrote:
Hi Ayan,
Hi Julien,
I need a clarification.
In the title you are using AArch32 but below you are using...
On 31/10/2022 15:13, Ayan Kumar Halder wrote:
v->arch.vmpidr is assigned to uint64_t variable. This is to enable
left shifts
for Aarch32 so that one can extract affinity bits.
... Aarch32. The naming also seem to be inconsistent across your
series. AFAIU, it should be AArch32. So please look at all your
commits and make sure you use the same everywhere.
Ack
This is then assigned to 'typer' so that the affinity bits form the
upper 32 bits.
Refer Arm IHI 0069H ID020922,
The upper 32 bits of GICR_TYPER represent the affinity
whereas the lower 32 bits represent the other bits (eg processor
number, etc).
Signed-off-by: Ayan Kumar Halder <ayankuma@xxxxxxx>
---
Changes from :-
1. v1 - Assigned v->arch.vmpidr to "uint64_t vmpdir". Then, we can use
MPIDR_AFFINITY_LEVEL macros to extract the affinity value.
xen/arch/arm/vgic-v3.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 3f4509dcd3..e5e6f2c573 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -191,13 +191,15 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct
vcpu *v, mmio_info_t *info,
case VREG64(GICR_TYPER):
{
uint64_t typer, aff;
+ uint64_t vmpidr = v->arch.vmpidr;
if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
- aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
- MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
- MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 |
- MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32);
+ aff = (MPIDR_AFFINITY_LEVEL(vmpidr, 3) << 56 |
Shouldn't we #ifdef this level for 32-bit? Or maybe check if the
domain is 64-bit so we are using consistently regardless of the
hypervisor bitness.
We have typecasted "v->arch.vmpidr" (which is 32bit for AArch32 and
64bit for AArch64) to vmpidr (uint64_t).
So, we don't need to have any #ifdef for AArch32 or AArch64.
Please let me know if I am missing something.
Also, GICR_TYPER is 64 bit for AArch32 and AArch64.
- Ayan
+ MPIDR_AFFINITY_LEVEL(vmpidr, 2) << 48 |
+ MPIDR_AFFINITY_LEVEL(vmpidr, 1) << 40 |
+ MPIDR_AFFINITY_LEVEL(vmpidr, 0) << 32);
typer = aff;
+
Spurious change?
/* We use the VCPU ID as the redistributor ID in bits[23:8] */
typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT;
Cheers,
|
