[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re:
On 18/11/2022 07:47, Michal Orzel wrote: On 18/11/2022 03:00, Jiamei Xie wrote:Date: Thu, 17 Nov 2022 11:07:12 +0800 Subject: [PATCH] xen/arm: vpl011: Make access to DMACR write-ignore When the guest kernel enables DMA engine with "CONFIG_DMA_ENGINE=y", Linux SBSA PL011 driver will access PL011 DMACR register in some functions. As chapter "B Generic UART" in "ARM Server Base System Architecture"[1] documentation describes, SBSA UART doesn't support DMA. In current code, when the kernel tries to access DMACR register, Xen will inject a data abort: Unhandled fault at 0xffffffc00944d048 Mem abort info: ESR = 0x96000000 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x00: ttbr address size fault Data abort info: ISV = 0, ISS = 0x00000000 CM = 0, WnR = 0 swapper pgtable: 4k pages, 39-bit VAs, pgdp=0000000020e2e000 [ffffffc00944d048] pgd=100000003ffff803, p4d=100000003ffff803, pud=100000003ffff803, pmd=100000003fffa803, pte=006800009c090f13 Internal error: ttbr address size fault: 96000000 [#1] PREEMPT SMP ... Call trace: pl011_stop_rx+0x70/0x80 tty_port_shutdown+0x7c/0xb4 tty_port_close+0x60/0xcc uart_close+0x34/0x8c tty_release+0x144/0x4c0 __fput+0x78/0x220 ____fput+0x1c/0x30 task_work_run+0x88/0xc0 do_notify_resume+0x8d0/0x123c el0_svc+0xa8/0xc0 el0t_64_sync_handler+0xa4/0x130 el0t_64_sync+0x1a0/0x1a4 Code: b9000083 b901f001 794038a0 8b000042 (b9000041) ---[ end trace 83dd93df15c3216f ]--- note: bootlogd[132] exited with preempt_count 1 /etc/rcS.d/S07bootlogd: line 47: 132 Segmentation fault start-stop-daemon As discussed in [2], this commit makes the access to DMACR register write-ignore as an improvement.As discussed earlier, if we decide to improve vpl011 (for now only Stefano shared his opinion), then we need to mark *all* the PL011 registers that are not part of SBSA ar RAZ/WI. I would be fine to that. But I would like us to print a message using XENLOG_G_DEBUG to catch any OS that would touch those registers. Cheers, -- Julien Grall
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