[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [XEN v3 04/12] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32


  • To: Julien Grall <julien@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • From: Ayan Kumar Halder <ayankuma@xxxxxxx>
  • Date: Mon, 28 Nov 2022 09:56:15 +0000
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WsZNMND5Nl7inyH0pKOhR0yFnlOgfOG790G2NUvqmPI=; b=cdpQ9onCN51z83ydq+zYtTkKHSr61GYxII0gn+3Oz1kfdzB/Z6Q/k6+OPP6eFESHsDFvTe8wvrN90T/aMbXNDlryRlnfZ2rSAem6ZmSIFL6TXsJc4B16XNknOpRTGpbIhTkwb2EYyE11ZFPSMgUS1YIxz22asFx2Pr4BfLeId4GEUdAjMlJMnKgSJvY/btYI6BkjcYcK8r7jBq23TmhL21e41iDc9OxmCSd2v40jcEKdaJ1Zpwtv1JaZ5G93AldDeopZQUAnVnIAu8YBz/mBp330nvKJM18u+xtru5gzJDflmng/kc1110QVxeGhiNEjLRDGO8E1Stqd9D1+Mw5b5w==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VHWLs3rUpJkfBZeiMUes2lqx9yriFePJib+jjAlFKUC31Hzh6egUNI5DlO8WwsS8FLOUvuRA5hQHpMdf2i4zVUrajubEUZIOFfCJSBhd9uV0BVRoc8P87zzbhZylVnO5jVgER1/r8+6Ql/RgE83FZz/HU1ao8R62oioPrp98Sgw3pV61oQ4NCoEA7q4OIDC8jQoTp9NivBzAuI9anlErD0ReLIqpoIm3k9kV8khES5Q7g5MXrGas+3pJ0N0YgvjIaN0qvWc7mjhjwd/FNxPQgq5oOZunDyIQlz21zaORgGxPITQzIV+jMvp1LXi+SZZin61X+t6guefGs+yiusyBAA==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
  • Cc: sstabellini@xxxxxxxxxx, stefanos@xxxxxxxxxx, Volodymyr_Babchuk@xxxxxxxx, bertrand.marquis@xxxxxxx, michal.orzel@xxxxxxx, jgrall@xxxxxxxxxx, burzalodowa@xxxxxxxxx
  • Delivery-date: Mon, 28 Nov 2022 09:56:40 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>


On 22/11/2022 20:37, Julien Grall wrote:
Hi Ayan,

Hi Julien,

I need a clarification.


On 11/11/2022 14:17, Ayan Kumar Halder wrote:
Refer ARM DDI 0487I.a ID081822, G8-9650, G8.2.113
Aff3 does not exist on AArch32.
Also, refer ARM DDI 0406C.d ID040418, B4-1644, B4.1.106
Aff3 does not exist on Armv7 (ie arm32).

Thus, access to aff3 have been contained within "#ifdef CONFIG_ARM_64".
Also, v->arch.vmpidr is a 32 bit register on AArch32. So, we have copied it to
'uint64_t vmpidr' to perform the shifts.

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
---

Changes from :-
v1 - Assigned v->arch.vmpidr to "uint64_t vmpdir". Then, we can use
MPIDR_AFFINITY_LEVEL macros to extract the affinity value.

v2 - 1. "MPIDR_AFFINITY_LEVEL(vmpidr, 3)" is contained within
"#ifdef CONFIG_ARM_64".
2. Updated commit message.

  xen/arch/arm/vgic-v3.c | 12 ++++++++----
  1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 3f4509dcd3..a7a935ff57 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -191,12 +191,16 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info,
      case VREG64(GICR_TYPER):
      {
          uint64_t typer, aff;
+        uint64_t vmpidr = v->arch.vmpidr;

The type-widening here deserve an in-code comment. Otherwise, it would be easier for someone to decide to open-code v->arch.vmpidr again.

Does this comment look fine ?

        /*
         * This is to enable shifts greater than 32 bits which would have
         * otherwise caused overflow (as v->arch.vmpidr is 32 bit on AArch32).
         */
        uint64_t vmpidr = v->arch.vmpidr;

- Ayan


            if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
-        aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 |
-               MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 |
-               MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 |
-               MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32);
+        aff = (
+#ifdef CONFIG_ARM_64
+               MPIDR_AFFINITY_LEVEL(vmpidr, 3) << 56 |
+#endif
+               MPIDR_AFFINITY_LEVEL(vmpidr, 2) << 48 |
+               MPIDR_AFFINITY_LEVEL(vmpidr, 1) << 40 |
+               MPIDR_AFFINITY_LEVEL(vmpidr, 0) << 32);
          typer = aff;
          /* We use the VCPU ID as the redistributor ID in bits[23:8] */
          typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT;

Cheers,




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.