[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[XEN v1] Xen: Enable compilation when PADDR_BITS == BITS_PER_LONG


  • To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
  • Date: Thu, 1 Dec 2022 10:03:09 +0000
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0LuPZLlNaOwbp7Ht+jXJOV/B2fhftFNV1Gl0W7OOUhc=; b=ZnxjucvLj6F1Jxrtm7vV3qfMqhzY9vUGSigv3eJpzLXjoppGp7ks9Wq12dqJ64TPzF3nn/+2asFx9Jp0Xmjguj7mQBiVI7xhwbwHqrVF6ug/1CsgDPZl2WVIw1fnnj8BpUfk5K1tVpGOjbMlmqIyzHAkJncF0H5kR747XagWUpYU7QeYGa7nYugJQfatTX5CMxsi6ylJHVgDc4rj6Rr/z/85cxyksjwhb6LHK0wGOiaETJo+44AfOGkOYwFHslORJF10sWBCmBLz3T9zGhIjvqbalq7tPQUTOFyPvDVSwjFWc63hiwQvrtdWVj0fpiuSFdpqgGpsBqBJ/ttio4gwfQ==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ghp8pRU3PRaaVw1ubs/nsj4Lm20s9+knq7CyQDVpvuG5lasAisyD5mg3kohjaB6Kd5B/042KTouhaTJR2W2K4avxXV6WmhrqdHTViqp8ymHgpCxiRcIvXP76kxUDSGnF7PW4ouToyf41EwFCBdTDVysxTDYGRehLwKFHjKjoP4VkryI3ulYfk3UzMja0zlIA1SsgsvMvfVOR4ZfRqyzEBpOVmRIid5p9K23DSZ5JD5NnaBPyS2HZp2Xg+x/5CH/C4Pj8hVfd0FCXH50eHdpmNP/1Hsqb0Z4rfIRjGOMbLs8GuF7owH3lAZCvMYzRLyYbL2YlGzFqiRFTY3KIfQPoPA==
  • Cc: <sstabellini@xxxxxxxxxx>, <stefanos@xxxxxxxxxx>, <julien@xxxxxxx>, <andrew.cooper3@xxxxxxxxxx>, <george.dunlap@xxxxxxxxxx>, <jbeulich@xxxxxxxx>, <bobbyeshleman@xxxxxxxxx>, <alistair.francis@xxxxxxx>, <connojdavis@xxxxxxxxx>, <wl@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
  • Delivery-date: Thu, 01 Dec 2022 10:07:16 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

It is possible for a pointer to represent physical memory of the same size.
In other words, a 32 bit pointer can represent 32 bit addressable physical
memory.
Thus, issue a compilation failure only when the count of physical address bits
is greater than BITS_PER_LONG (ie count of bits in void*).

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
---

Currently this change will not have any impact on the existing architectures.
The following table illustrates PADDR_BITS vs BITS_PER_LONG of different archs

------------------------------------------------
| Arch      |   PADDR_BITS    |   BITS_PER_LONG |
------------------------------------------------
| Arm_64    |   48            |   64            |
| Arm_32    |   40            |   32            |
| RISCV_64  |   Don't know    |   64            |
| x86       |   52            |   64            |
-------------------------------------------------

However, this will change when we introduce a platform (For eg Cortex-R52) which
supports 32 bit physical address and BITS_PER_LONG.
Thus, I have introduced this change as I don't see it causing a regression on
any of the supported platforms.

 xen/common/page_alloc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index 62afb07bc6..cd390a0956 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -2245,7 +2245,7 @@ void __init xenheap_max_mfn(unsigned long mfn)
 {
     ASSERT(!first_node_initialised);
     ASSERT(!xenheap_bits);
-    BUILD_BUG_ON(PADDR_BITS >= BITS_PER_LONG);
+    BUILD_BUG_ON(PADDR_BITS > BITS_PER_LONG);
     xenheap_bits = min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS);
     printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits);
 }
-- 
2.17.1




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.