[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH v4 02/14] xen/arm64: flushtlb: Implement the TLBI repeat workaround for TLB flush by VA
- To: Julien Grall <julien@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Henry Wang <Henry.Wang@xxxxxxx>
- Date: Fri, 13 Jan 2023 13:22:16 +0000
- Accept-language: zh-CN, en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ujhcm3PSPgw4bvKyeCbe7lP+sd7EjCAeMcV73gd2RxQ=; b=SnkbN1hNgDJWuXeVDH831fGbzl5ek9NzQZ5/qufITTCHJRPyrFUzii2nuOs8k5fa2/EkxXv9QxMtTyfuuUfB+VklkDAe2RttEoui8dOrDACHTeewOPBiMHYlGoQ0gRtcKtSQP9I0ntykQ5phJd+94ijS8ZEs8X8wbooZ8Nzg4zPHp9iu9oELr8nxm6RXalOFCrNX3x8rli8F2r7Mm06uRa6Y9I9+W++oAIO4+FnmHtXrV0Y9JOpxqyztDTdfc6Oa1iDkhVJSlpgYA4ibNRGW2HmHPf4J5bSTLwL9usgEPq0bBi9ICLsfUAI4CBVfyA1kA7VT4WGmkBnQxRUp6Sn/6A==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VfSwjdbhX1FGjdaz/3KXOzoyJc4ho119BvbgiWJ4VTFDVTw6cm30r/g8hEfjds6swWuRiTuGtnm2bB4MDE/YiuRtzKCkSpzW9eJtLF5OKxbzXvqvJjDBu2QOuYDt4K6lwCT95SnGouslDzOXC051Zx5lTs5MQYaPD2PVEADn3qN0Xs5ojbs0q7gule3dDMJPm2V5OG5/WICjntUmU9F+KIMJU8AUBchTa5E/mWP7L7vYLBdwnATPnKhelUm0IeSEwTUXBPnmMPJR4u0IhLjAo0ld8xm5E2wsRqxzFb0+ORkmdnOGZTMsjSA0Non9o9NmmLDrY3pNhIigaaiLxK99PQ==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: Luca Fancellu <Luca.Fancellu@xxxxxxx>, Julien Grall <jgrall@xxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>
- Delivery-date: Fri, 13 Jan 2023 13:22:39 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Thread-index: AQHZJzd61qXKtXVMLEiNLp0lWxtmx66cPDEA
- Thread-topic: [PATCH v4 02/14] xen/arm64: flushtlb: Implement the TLBI repeat workaround for TLB flush by VA
Hi Julien,
> -----Original Message-----
> Subject: [PATCH v4 02/14] xen/arm64: flushtlb: Implement the TLBI repeat
> workaround for TLB flush by VA
>
> From: Julien Grall <jgrall@xxxxxxxxxx>
>
> Looking at the Neoverse N1 errata document, it is not clear to me
> why the TLBI repeat workaround is not applied for TLB flush by VA.
>
> The TBL flush by VA helpers are used in flush_xen_tlb_range_va_local()
> and flush_xen_tlb_range_va(). So if the range size if a fixed size smaller
> than a PAGE_SIZE, it would be possible that the compiler remove the loop
> and therefore replicate the sequence described in the erratum 1286807.
>
> So the TLBI repeat workaround should also be applied for the TLB flush
> by VA helpers.
>
> Fixes: 22e323d115d8 ("xen/arm: Add workaround for Cortex-A76/Neoverse-
> N1 erratum #1286807")
> Signed-off-by: Julien Grall <jgrall@xxxxxxxxxx>
> Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
>
> ----
> This was spotted while looking at reducing the scope of the memory
> barriers. I don't have any HW affected.
Seeing this scissors line comment, I tried to test this patch using basically
the same approach that I did for patch#1 on every board that I can find,
including some Neoverse N1 boards, and this patch looks good, so:
Tested-by: Henry Wang <Henry.Wang@xxxxxxx>
Kind regards,
Henry
|
