Re: [XEN v2 07/11] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Tue, 17 Jan 2023, Ayan Kumar Halder wrote:
> Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9,
> SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use
> writeq_relaxed_non_atomic() to write to it instead of invoking
> writel_relaxed() twice for lower half and upper half of the register.
> 
> This also helps us as p2maddr is 'paddr_t' (which may be u32 in future).
> Thus, one can assign p2maddr to a 64 bit register and do the bit
> manipulations on it, to generate the value for SMMU_CBn_TTBR0.
> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>

Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>


> ---
> Changes from -
> 
> v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations 
> required to support 32bit paddr".
> Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic
> fashion.
> 
>  xen/drivers/passthrough/arm/smmu.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/xen/drivers/passthrough/arm/smmu.c 
> b/xen/drivers/passthrough/arm/smmu.c
> index 0c89cb644e..84b6803b4e 100644
> --- a/xen/drivers/passthrough/arm/smmu.c
> +++ b/xen/drivers/passthrough/arm/smmu.c
> @@ -500,8 +500,7 @@ enum arm_smmu_s2cr_privcfg {
>  #define ARM_SMMU_CB_SCTLR            0x0
>  #define ARM_SMMU_CB_RESUME           0x8
>  #define ARM_SMMU_CB_TTBCR2           0x10
> -#define ARM_SMMU_CB_TTBR0_LO         0x20
> -#define ARM_SMMU_CB_TTBR0_HI         0x24
> +#define ARM_SMMU_CB_TTBR0            0x20
>  #define ARM_SMMU_CB_TTBCR            0x30
>  #define ARM_SMMU_CB_S1_MAIR0         0x38
>  #define ARM_SMMU_CB_FSR                      0x58
> @@ -1084,6 +1083,7 @@ static void arm_smmu_flush_pgtable(struct 
> arm_smmu_device *smmu, void *addr,
>  static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
>  {
>       u32 reg;
> +     u64 reg64;
>       bool stage1;
>       struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
>       struct arm_smmu_device *smmu = smmu_domain->smmu;
> @@ -1178,12 +1178,13 @@ static void arm_smmu_init_context_bank(struct 
> arm_smmu_domain *smmu_domain)
>       dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n",
>                  smmu_domain->cfg.domain->domain_id, p2maddr);
>  
> -     reg = (p2maddr & ((1ULL << 32) - 1));
> -     writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
> -     reg = (p2maddr >> 32);
> +     reg64 = p2maddr;
> +
>       if (stage1)
> -             reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
> -     writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
> +             reg64 |= (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << 
> TTBRn_HI_ASID_SHIFT))
> +                      << 32);
> +
> +     writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0);
>  
>       /*
>        * TTBCR
> -- 
> 2.17.1
>