[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v3 00/14] RISCV basic exception handling implementation
The patch series is based on another one [Basic early_printk and smoke test implementation] and [introduce generic implementation of macros from bug.h] which haven't been commited yet. The patch series provides a basic implementation of exception handling. It can do only basic things such as decode a cause of an exception, save/restore registers and execute "wfi" instruction if an exception can not be handled. To verify that exception handling works well it was implemented macros from <asm/bug.h> such as BUG/WARN/run_in_exception/assert_failed. The implementation of macros is used "ebreak" instruction and set up bug frame tables for each type of macros. Also it was implemented register save/restore to return and continue work after WARN/run_in_exception. Not all functionality of the macros was implemented as some of them require hard-panic the system which is not available now. Instead of hard-panic 'wfi' instruction is used but it should be definitely changed in the neareset future. It wasn't implemented show_execution_state() and stack trace discovering as it's not necessary now. --- Changes in V3: - Change the name of config RISCV_ISA_RV64IMA to RISCV_ISA_RV64G as instructions from Zicsr and Zifencei extensions aren't part of I extension any more. - Rebase the patch "xen/riscv: introduce an implementation of macros from <asm/bug.h>" on top of patch series [introduce generic implementation of macros from bug.h] - Update commit messages --- Changes in V2: - take the latest riscv_encoding.h from OpenSBI, update it with Xen related changes, and update the commit message with "Origin:" tag and the commit message itself. - add "Origin:" tag to the commit messag of the patch [xen/riscv: add <asm/csr.h> header]. - Remove the patch [xen/riscv: add early_printk_hnum() function] as the functionality provided by the patch isn't used now. - Refactor prcoess.h: move structure offset defines to asm-offsets.c, change register_t to unsigned long. - Refactor entry.S to use offsets defined in asm-offsets.C - Rename {__,}handle_exception to handle_trap() and do_trap() to be more consistent with RISC-V spec. - Merge the pathc which introduces do_unexpected_trap() with the patch [xen/riscv: introduce exception handlers implementation]. - Rename setup_trap_handler() to trap_init() and update correspondingly the patches in the patch series. - Refactor bug.h, remove bug_instr_t type from it. - Refactor decode_trap_cause() function to be more optimization-friendly. - Add two new empty headers: <cache.h> and <string.h> as they are needed to include <xen/lib.h> which provides ARRAY_SIZE and other macros. - Code style fixes. --- Oleksii Kurochko (14): xen/riscv: change ISA to r64G xen/riscv: add <asm/asm.h> header xen/riscv: add <asm/riscv_encoding.h header xen/riscv: add <asm/csr.h> header xen/riscv: introduce empty <asm/string.h> xen/riscv: introduce empty <asm/cache.h> xen/riscv: introduce exception context xen/riscv: introduce exception handlers implementation xen/riscv: introduce decode_cause() stuff xen/riscv: mask all interrupts xen/riscv: introduce trap_init() xen/riscv: introduce an implementation of macros from <asm/bug.h> xen/riscv: test basic handling stuff automation: modify RISC-V smoke test automation/scripts/qemu-smoke-riscv64.sh | 2 +- xen/arch/riscv/Kconfig | 14 +- xen/arch/riscv/Makefile | 2 + xen/arch/riscv/arch.mk | 2 +- xen/arch/riscv/entry.S | 94 ++ xen/arch/riscv/include/asm/asm.h | 54 ++ xen/arch/riscv/include/asm/bug.h | 38 + xen/arch/riscv/include/asm/cache.h | 6 + xen/arch/riscv/include/asm/csr.h | 84 ++ xen/arch/riscv/include/asm/processor.h | 82 ++ xen/arch/riscv/include/asm/riscv_encoding.h | 927 ++++++++++++++++++++ xen/arch/riscv/include/asm/string.h | 6 + xen/arch/riscv/include/asm/traps.h | 14 + xen/arch/riscv/riscv64/asm-offsets.c | 53 ++ xen/arch/riscv/riscv64/head.S | 5 + xen/arch/riscv/setup.c | 22 +- xen/arch/riscv/traps.c | 233 +++++ xen/arch/riscv/xen.lds.S | 10 + 18 files changed, 1640 insertions(+), 8 deletions(-) create mode 100644 xen/arch/riscv/entry.S create mode 100644 xen/arch/riscv/include/asm/asm.h create mode 100644 xen/arch/riscv/include/asm/bug.h create mode 100644 xen/arch/riscv/include/asm/cache.h create mode 100644 xen/arch/riscv/include/asm/csr.h create mode 100644 xen/arch/riscv/include/asm/processor.h create mode 100644 xen/arch/riscv/include/asm/riscv_encoding.h create mode 100644 xen/arch/riscv/include/asm/string.h create mode 100644 xen/arch/riscv/include/asm/traps.h create mode 100644 xen/arch/riscv/traps.c -- 2.39.0
|
Lists.xenproject.org is hosted with RackSpace, monitoring our |