[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v2 0/8] x86/mtrr: fix handling with PAT but without MTRR
On 16.02.23 00:22, Linus Torvalds wrote: On Wed, Feb 15, 2023 at 12:25 AM Juergen Gross <jgross@xxxxxxxx> wrote:The problem arises in case a large mapping is spanning multiple MTRRs, even if they define the same caching type (uniform is set to 0 in this case).Oh, I think then you should fix uniform to be 1. IOW, we should not think "multiple MTRRs" means "non-uniform". Only "different actual memory types" should mean non-uniformity. Thanks for confirmation. I completely agree. If I remember correctly, there were good reasons to have overlapping MTRR's. In fact, you can generate a single MTRR that described a memory ttype that wasn't even contiguous if you had odd memory setups. Intel definitely defines how overlapping MTRR's work, and "same types overlaps" is documented as a real thing. Yes. And it is handled wrong in current code. Handling it correctly will require quite some reworking of the code, which I've already started to work on. I will defer the pud_set_huge()/ pmd_set_huge() modifying patch to after this rework. Juergen Attachment:
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