[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[XEN v4 08/11] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32"


  • To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
  • Date: Tue, 21 Mar 2023 14:03:54 +0000
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Xotrsbhl/FLSUoI3qOBJKeSy4Rd9/LSb5Psg/+0wEqU=; b=bUzfJM1zV+yvkVC0kxWJLCcsItL4rvcTP+U5ZswMGS08JAbCGvfUgR0AB5NPTS6cXOxJbhtbezO7B76cte3v7VV6Amj3VwU7LCKrWDxGEYW38UFSbDaq+5oEFS3vOyK/hSmFR2pHC9f59rEqcWxK0fwlvVFoZgvnMIkK47JpwXWEpB9IPvxU0evVpa1uS7bDPHDoRyXef72INohWEtgWAm3DeYYk5Pwn0Fz32agFv2H6qEov/U++GS8wD7NkK0T8Gddixs8x2u4sL84MKryItcqlqeySiGQP5PN5hr55RVk0EjwvYtiLsj/LegVEr/8IZWIp+afdU+BefNwXRQcr8Q==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eKQkFU6qLgeXsZSkzbsYKSUCw+eAg2PjpPUJwphMFl2Fd4cN2E7ZbdPCGhegR9Rmas1laObM0UB6mRdIhwutaelI704zce2gYVcfr1Q8O41Oq1uXIQRI4xvj0En+SIyyLoPOKLhLBAbuRo/u4FJipeLwHMBbt5w/JkjjARmTGH9JdBC6y1/lp4JYOEYMWhukK2ae2wEL3s+NFmGgZM45z8i3WDJ4UkmMQB0p/jeNNQDTykphkQZWuTHNMq+dnTr4z3YbIpPDXPVJBTEwDCofBkh2MNcJwuTXD+lM+kupjjNo8GlLn/6zbMQqVxPpHZgxsotyK05D1y3RHHT4rutVww==
  • Cc: <sstabellini@xxxxxxxxxx>, <stefano.stabellini@xxxxxxx>, <julien@xxxxxxx>, <Volodymyr_Babchuk@xxxxxxxx>, <bertrand.marquis@xxxxxxx>, <andrew.cooper3@xxxxxxxxxx>, <george.dunlap@xxxxxxxxxx>, <jbeulich@xxxxxxxx>, <wl@xxxxxxx>, <rahul.singh@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
  • Delivery-date: Tue, 21 Mar 2023 14:05:33 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

As the previous patch introduces CONFIG_PHYS_ADDR_T_32 to support 32 bit
physical addresses, the code specific to "Large Physical Address Extension"
(ie LPAE) should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32".

Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t"
unsigned int extbase1:4;    /* Extended base address, PA[35:32] */
unsigned int extbase2:4;    /* Extended base address, PA[39:36] */

Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses
are supported.

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
Acked-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
Changes from -
v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to 
support 32bit paddr".

v2 - 1. Reordered this patch so that it appears after CONFIG_ARM_PA_32 is
introduced (in 6/9).

v3 - 1. Updated the commit message.
2. Added Ack.

 xen/arch/arm/guest_walk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
index 43d3215304..c80a0ce55b 100644
--- a/xen/arch/arm/guest_walk.c
+++ b/xen/arch/arm/guest_walk.c
@@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v,
             mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1;
             *ipa = gva & mask;
             *ipa |= (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_SHIFT;
+#ifndef CONFIG_PHYS_ADDR_T_32
             *ipa |= (paddr_t)(pte.supersec.extbase1) << 
L1DESC_SUPERSECTION_EXT_BASE1_SHIFT;
             *ipa |= (paddr_t)(pte.supersec.extbase2) << 
L1DESC_SUPERSECTION_EXT_BASE2_SHIFT;
+#endif /* CONFIG_PHYS_ADDR_T_32 */
         }
 
         /* Set permissions so that the caller can check the flags by herself. 
*/
-- 
2.17.1




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.