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Re: [XEN v4 06/11] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0
- To: Julien Grall <julien@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Ayan Kumar Halder <ayankuma@xxxxxxx>
- Date: Mon, 3 Apr 2023 13:49:44 +0100
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On 30/03/2023 22:27, Julien Grall wrote:
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Hi Ayan,
Hi Julien,
On 21/03/2023 14:03, Ayan Kumar Halder wrote:
Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9,
SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use
writeq_relaxed_non_atomic() to write to it instead of invoking
writel_relaxed() twice for lower half and upper half of the register.
This also helps us as p2maddr is 'paddr_t' (which may be u32 in future).
Thus, one can assign p2maddr to a 64 bit register and do the bit
manipulations on it, to generate the value for SMMU_CBn_TTBR0.
Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
The tags should be ordered in a timeline. So Signed-off-by should be
first.
Ack. I will take care henceforth.
I am happy to do it on commit if you can confirm that this patch doesn't
dependent on the patches before.
Yes, please commit this patch as it is independent of the patch series.
- Ayan
Cheers,
--
Julien Grall
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