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Re: [PATCH] x86/hvm: Disallow CR0.PG 1->0 transitions when CS.L=1
- To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Thu, 13 Apr 2023 13:08:34 +0100
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- Cc: Jan Beulich <JBeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Thu, 13 Apr 2023 12:09:07 +0000
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- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 12/04/2023 7:35 pm, Andrew Cooper wrote:
> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
> index 1454c1732d95..3c8d28a2d8be 100644
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -2340,6 +2340,21 @@ int hvm_set_cr0(unsigned long value, bool may_defer)
> }
> else if ( !(value & X86_CR0_PG) && (old_value & X86_CR0_PG) )
> {
> + struct segment_register cs;
> +
> + hvm_get_segment_register(v, x86_seg_cs, &cs);
> +
> + /*
> + * Intel documents a #GP fault in this case, and VMEntry checks
> reject
> + * it as a valid state. AMD permits the state transition, and hits
> + * SHUTDOWN immediately thereafter. Follow the Intel behaviour.
> + */
> + if ( cs.l )
It occurs to me that this needs to be qualified with LME first, because
cs.l is software-available outside of long mode.
~Andrew
> + {
> + HVM_DBG_LOG(DBG_LEVEL_1, "Guest attempts to clear CR0.PG while
> CS.L=1");
> + return X86EMUL_EXCEPTION;
> + }
> +
> if ( hvm_pcid_enabled(v) )
> {
> HVM_DBG_LOG(DBG_LEVEL_1, "Guest attempts to clear CR0.PG "
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