[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v5 05/12] arm/sve: save/restore SVE context switch
> On 13 Apr 2023, at 14:11, Julien Grall <julien@xxxxxxx> wrote: > > > > On 12/04/2023 10:49, Luca Fancellu wrote: >> Save/restore context switch for SVE, allocate memory to contain >> the Z0-31 registers whose length is maximum 2048 bits each and >> FFR who can be maximum 256 bits, the allocated memory depends on >> how many bits is the vector length for the domain and how many bits >> are supported by the platform. >> Save P0-15 whose length is maximum 256 bits each, in this case the >> memory used is from the fpregs field in struct vfp_state, >> because V0-31 are part of Z0-31 and this space would have been >> unused for SVE domain otherwise. >> Create zcr_el{1,2} fields in arch_vcpu, initialise zcr_el2 on vcpu >> creation given the requested vector length and restore it on >> context switch, save/restore ZCR_EL1 value as well. >> Remove headers from sve.c that are already included using >> xen/sched.h. > I dislike this because ... > >> diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c >> index 78f7482619da..5485648850a0 100644 >> --- a/xen/arch/arm/arm64/sve.c >> +++ b/xen/arch/arm/arm64/sve.c >> @@ -5,14 +5,29 @@ >> * Copyright (C) 2022 ARM Ltd. >> */ >> -#include <xen/types.h> >> -#include <asm/cpufeature.h> > > ... it is not entirely obvious that sched.h will import asm/cpufeatures.h. > This could easily change in the future and would only require us to re-add > those includes. Ok I will reintroduce #include <asm/cpufeature.h>, do I understand correctly that is the only header you would like me to retain? > >> +#include <xen/sched.h> >> +#include <xen/sizes.h> > #include <asm/arm64/sve.h> >> -#include <asm/arm64/sysregs.h> >> -#include <asm/processor.h> >> -#include <asm/system.h> >> extern unsigned int sve_get_hw_vl(void); >> +extern void sve_save_ctx(uint64_t *sve_ctx, uint64_t *pregs, int save_ffr); >> +extern void sve_load_ctx(uint64_t const *sve_ctx, uint64_t const *pregs, >> + int restore_ffr); >> + >> +static inline unsigned int sve_zreg_ctx_size(unsigned int vl) >> +{ >> + /* >> + * Z0-31 registers size in bytes is computed from VL that is in bits, >> so VL >> + * in bytes is VL/8. >> + */ >> + return (vl / 8U) * 32U; >> +} >> + >> +static inline unsigned int sve_ffrreg_ctx_size(unsigned int vl) >> +{ >> + /* FFR register size is VL/8, which is in bytes (VL/8)/8 */ >> + return (vl / 64U); >> +} >> register_t compute_max_zcr(void) >> { >> @@ -60,3 +75,46 @@ unsigned int get_sys_vl_len(void) >> return ((system_cpuinfo.zcr64.bits[0] & ZCR_ELx_LEN_MASK) + 1U) * >> SVE_VL_MULTIPLE_VAL; >> } >> + >> +int sve_context_init(struct vcpu *v) >> +{ >> + unsigned int sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl); >> + uint64_t *ctx = _xzalloc(sve_zreg_ctx_size(sve_vl_bits) + >> + sve_ffrreg_ctx_size(sve_vl_bits), >> + L1_CACHE_BYTES); >> + >> + if ( !ctx ) >> + return -ENOMEM; >> + >> + v->arch.vfp.sve_context = ctx; >> + >> + return 0; >> +} >> + >> +void sve_context_free(struct vcpu *v) >> +{ >> + xfree(v->arch.vfp.sve_context); >> +} > > Please use XFREE(). Sure I’ll do > > Cheers, > > -- > Julien Grall
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