[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 0/5] x86: reduce cache flushing overhead
- To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 19 Apr 2023 12:43:28 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1WLiDF52gwlGsA56jTGQEg+iCy+r7F/0Tm2Kl2/K1xA=; b=IgNZaSQkmnY7xhBhJQPJxsy6rO1B9sx999f5NrHyOWIaYzWEdOgstJc1roINwTtvshnCC1jZN0VhbEqnzjJXTg/F6402olEJ4C9wNLbdMzF/raX/2dQNmQm85qV+EVIlWWyc/UOkDYl/YVBd6lWQiVNT2i9iNtgbZoACCB1fSlg9XwnGsO7sKW0/+UOvmNRuiYTPOO4NtZJyt9FPliDL8TMPM6zgEkimGRkoox7oTYSA5a/+HNbO6YsgUWgSgH5UpEx5aXNNv/ZkzEwOUaacYlvmKKqC5VvKMq/nScZKzx8LkNVriFdVjBlzmFUgkLZWMGY+kLXq4HKDLKOlKrfbGA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nWZusUWWS4XnvYn3sYaFSAyrB+noZ9zD46RCHxst2erhSvm6/hC1vRBx4Z/7w6TR+OitJit7Nc8C+289fZ6aZAWg36NqqyA6ysDNBKMV3MmtoGE4rckUPa7pXUYT0reudupigBsGkVXVPylaK7vN+3zqbWpbLJ5/jbppOa4H2XWj2rCtPKQ2oDBVUNb9bnbj/TEfM/qu8LcXAWLuHhwvHX2spoVcerE/9tmtbJK+tcFTGGcOWkN9vjLZgJILZBWxD7HSSi1XivKrnXZqlBoZYEAxUfm4GJ4e6aXOLWtTiZ7PmbSq260+ZphxC7gr2eKX+erzgB34wWiKxTOXLWvP7g==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Wed, 19 Apr 2023 10:43:35 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
..., first and foremost by using cache write-back operations instead
of flushing ones when available (and sufficient for the purpose).
In the context of making the last patch I started wondering whether
for PV we don't flush (write back) too little for MMUEXT_FLUSH_CACHE:
Just like for HVM, pCPU-s a vCPU has run on before could still hold
data in their caches. (We clearly still flush / write back too much
in MMUEXT_FLUSH_CACHE_GLOBAL even with this series in place.) We also
can't call this the guest's responsibility, as it may not have any
means to have one of its vCPU-s run on the intended pCPU.
1: x86: support cache-writeback in flush_area_local() et al
2: x86/HVM: restrict guest-induced WBINVD to cache writeback
3: x86/PV: restrict guest-induced WBINVD (or alike) to cache writeback
4: VT-d: restrict iommu_flush_all() to cache writeback
5: x86/HVM: limit cache writeback overhead
Jan
|
