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[PATCH 7/7] x86: don't allow Dom0 access to ELCR ports
- To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 11 May 2023 14:08:09 +0200
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Thu, 11 May 2023 12:08:16 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Much like the other PIC ports, Dom0 has no business touching these. Even
our own uses are somewhat questionable, as the corresponding IO-APIC
code in Linux is enclosed in a CONFIG_EISA conditional; I don't think
there are any x86-64 EISA systems.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
RFC: For Linux'es (matching our) construct_default_ioirq_mptable() we
may need to permit read access at least for PVH, if such default
table construction is assumed to be sensible there in the first
place (we assume ACPI and no PIC for PVH Dom0, after all).
RFC: Linux further has ACPI boot code accessing ELCR
(acpi_pic_sci_set_trigger() and acpi_register_gsi_pic()), which we
have no equivalent of.
Taken together, perhaps the hiding needs to be limited to PVH Dom0?
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -503,6 +503,9 @@ int __init dom0_setup_permissions(struct
rc |= ioports_deny_access(d, 0xA0 + offs, 0xA1 + offs);
}
+ /* ELCR of both PICs. */
+ rc |= ioports_deny_access(d, 0x4D0, 0x4D1);
+
/* Interval Timer (PIT). */
for ( offs = 0, i = pit_alias_mask & -pit_alias_mask ?: 4;
offs <= pit_alias_mask; offs += i )
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