Re: [PATCH 2/3] x86: Add support for AMD's Automatic IBRS

[Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>]

On Fri, May 26, 2023 at 04:00:43PM +0100, Alejandro Vallejo wrote:
> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> index 74e3915a4d..09cfef2676 100644
> --- a/xen/arch/x86/setup.c
> +++ b/xen/arch/x86/setup.c
> @@ -2036,6 +2036,9 @@ void __init noreturn __start_xen(unsigned long mbi_p)
>          barrier();
>          wrmsrl(MSR_SPEC_CTRL, default_xen_spec_ctrl);
>          info->last_spec_ctrl = default_xen_spec_ctrl;
> +
> +        if ( cpu_has_auto_ibrs && (default_xen_spec_ctrl & SPEC_CTRL_IBRS) )
> +            write_efer(read_efer() | EFER_AIBRSE);
>      }
After thinking things through I think I'll get rid of this "delay AutoIBRS"
setting. I initially thought there might have been some handshake between
the newly created dom0 and Xen on this path, but that doesn't seem to be
the case. If so, I can remove some of this disjoint logic by setting AIBRSE
on the local EFER and trampoline_efer during init_speculation_mitigation.
Then the BSP will have the correct setting, the APs will pick it up on boot
and S3 wakeups will do the right thing too.

I'm assuming then bsp_delay_spec_ctrl is there mostly to delay STIBP for as
long as possible?

Alejandro