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Re: [PATCH v2 3/3] x86: Add support for AMD's Automatic IBRS
- To: Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 1 Jun 2023 12:35:16 +0200
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Thu, 01 Jun 2023 10:35:35 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 30.05.2023 15:58, Alejandro Vallejo wrote:
> @@ -1150,15 +1155,20 @@ void __init init_speculation_mitigations(void)
> }
> else
> {
> - /*
> - * Evaluate the safest Branch Target Injection mitigations to use.
> - * First, begin with compiler-aided mitigations.
> - */
This is the only place where BTI is spelled out, so ...
> - if ( IS_ENABLED(CONFIG_INDIRECT_THUNK) )
> + /* Evaluate the safest BTI mitigations with lowest overhead */
... I'd like to ask that you replace the acronym here. Then
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
> @@ -1357,7 +1367,9 @@ void __init init_speculation_mitigations(void)
> */
> if ( opt_rsb_hvm )
> {
> - setup_force_cpu_cap(X86_FEATURE_SC_RSB_HVM);
> + /* Automatic IBRS wipes the RSB for us on VMEXIT */
> + if ( !(ibrs && cpu_has_auto_ibrs) )
> + setup_force_cpu_cap(X86_FEATURE_SC_RSB_HVM);
I'll need to remember to adjust "x86: limit issuing of IBPB during context
switch" once this change has gone in, as there's a use of the bit for
other than alternatives patching.
Jan
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