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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v2 1/2] x86/boot: Clear XD_DISABLE from the early boot path
Intel CPUs have a bit in MSR_IA32_MISC_ENABLE that may prevent the NX bit
from being advertised. Clear it unconditionally if we can't find the NX
feature right away on boot.
The conditions for the MSR being read on early boot are (in this order):
* Long Mode is supported
* NX isn't advertised
* The vendor is Intel
The order of checks has been chosen carefully so a virtualized Xen on a
hypervisor that doesn't emulate that MSR (but supports NX) doesn't triple
fault trying to access the non-existing MSR.
While at it, make sure we use rdmsr_safe rather than rdmsrl in the
Intel-specific init path so we don't accidentally crash if the MSR isn't
emulated while Xen is virtualized.
Signed-off-by: Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>
---
xen/arch/x86/boot/head.S | 60 ++++++++++++++++++++++++----
xen/arch/x86/cpu/intel.c | 32 +++++++--------
xen/arch/x86/include/asm/msr-index.h | 2 +-
3 files changed, 69 insertions(+), 25 deletions(-)
diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index 09bebf8635..ce62eae6f3 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -142,8 +142,8 @@ efi_platform:
.section .init.text, "ax", @progbits
-bad_cpu:
- add $sym_offs(.Lbad_cpu_msg),%esi # Error message
+.Lbad_cpu:
+ add $sym_offs(.Lbad_cpu_msg),%esi
jmp .Lget_vtb
not_multiboot:
add $sym_offs(.Lbad_ldr_msg),%esi # Error message
@@ -647,15 +647,59 @@ trampoline_setup:
cpuid
1: mov %edx, CPUINFO_FEATURE_OFFSET(X86_FEATURE_LM) +
sym_esi(boot_cpu_data)
- /* Check for NX. Adjust EFER setting if available. */
+ /* Check for availability of long mode. */
+ bt $cpufeat_bit(X86_FEATURE_LM),%edx
+ jnc .Lbad_cpu
+
+ /* Check for NX */
bt $cpufeat_bit(X86_FEATURE_NX), %edx
+ jc .Lhas_nx_bit
+
+ /*
+ * NX appears to be unsupported, but it might be hidden.
+ *
+ * Intel CPUs (may) implement MSR_IA32_MISC_ENABLE. Among other
+ * things this MSR has a bit that artificially hides NX support in
+ * CPUID. Xen _really_ wants that feature enabled if present, so we
+ * have to determine if (a) the MSR exists and if so (b) clear the
+ * bit.
+ *
+ * For native boots this is perfectly fine because the MSR was
+ * introduced before Netburst, which was the first family to
+ * provide 64bit support. So we're safe simply accessing it as long
+ * as long mode support has already been checked.
+ *
+ * For the virtualized case the MSR might not be emulated though,
+ * so we make sure to do an initial check for NX in order to bypass
+ * this MSR read
+ */
+ xor %eax,%eax
+ cpuid
+ cmpl $X86_VENDOR_INTEL_EBX,%ebx
+ jnz .Lno_nx_bit
+ cmpl $X86_VENDOR_INTEL_EDX,%edx
+ jnz .Lno_nx_bit
+ cmpl $X86_VENDOR_INTEL_ECX,%ecx
+ jnz .Lno_nx_bit
+
+ /* Clear the XD_DISABLE bit */
+ movl $MSR_IA32_MISC_ENABLE, %ecx
+ rdmsr
+ btrl $2, %edx
jnc 1f
- orb $EFER_NXE >> 8, 1 + sym_esi(trampoline_efer)
-1:
+ wrmsr
+ orb $MSR_IA32_MISC_ENABLE_XD_DISABLE >> 32, 4 +
sym_esi(trampoline_misc_enable_off)
- /* Check for availability of long mode. */
- bt $cpufeat_bit(X86_FEATURE_LM),%edx
- jnc bad_cpu
+1: /* Check again for NX */
+ mov $0x80000001,%eax
+ cpuid
+ bt $cpufeat_bit(X86_FEATURE_NX), %edx
+ jnc .Lno_nx_bit
+
+.Lhas_nx_bit:
+ /* Adjust EFER is NX is present */
+ orb $EFER_NXE >> 8, 1 + sym_esi(trampoline_efer)
+.Lno_nx_bit:
/* Stash TSC to calculate a good approximation of time-since-boot */
rdtsc
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 168cd58f36..46b0cd8dbb 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -305,23 +305,23 @@ static void cf_check early_init_intel(struct cpuinfo_x86
*c)
c->x86_cache_alignment = 128;
/* Unmask CPUID levels and NX if masked: */
- rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
-
- disable = misc_enable & (MSR_IA32_MISC_ENABLE_LIMIT_CPUID |
- MSR_IA32_MISC_ENABLE_XD_DISABLE);
- if (disable) {
- wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
- bootsym(trampoline_misc_enable_off) |= disable;
- bootsym(trampoline_efer) |= EFER_NXE;
- }
+ if (rdmsr_safe(MSR_IA32_MISC_ENABLE, misc_enable) == 0) {
+ disable = misc_enable & (MSR_IA32_MISC_ENABLE_LIMIT_CPUID |
+ MSR_IA32_MISC_ENABLE_XD_DISABLE);
+ if (disable) {
+ wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
+ bootsym(trampoline_misc_enable_off) |= disable;
+ bootsym(trampoline_efer) |= EFER_NXE;
+ }
- if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
- printk(KERN_INFO "revised cpuid level: %d\n",
- cpuid_eax(0));
- if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {
- write_efer(read_efer() | EFER_NXE);
- printk(KERN_INFO
- "re-enabled NX (Execute Disable) protection\n");
+ if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
+ printk(KERN_INFO "revised cpuid level: %d\n",
+ cpuid_eax(0));
+ if (disable & MSR_IA32_MISC_ENABLE_XD_DISABLE) {
+ write_efer(read_efer() | EFER_NXE);
+ printk(KERN_INFO
+ "re-enabled NX (Execute Disable) protection\n");
+ }
}
/* CPUID workaround for Intel 0F33/0F34 CPU */
diff --git a/xen/arch/x86/include/asm/msr-index.h
b/xen/arch/x86/include/asm/msr-index.h
index 2749e433d2..4f861c0bb4 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -502,7 +502,7 @@
#define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22)
#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
-#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
+#define MSR_IA32_MISC_ENABLE_XD_DISABLE (_AC(1, ULL) << 34)
#define MSR_IA32_TSC_DEADLINE 0x000006E0
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
--
2.34.1
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