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RE: [PATCH 6/7] xen/arm: mm: Add missing ISB in xen_pt_update()
- To: Julien Grall <julien@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Henry Wang <Henry.Wang@xxxxxxx>
- Date: Tue, 20 Jun 2023 03:07:11 +0000
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- Cc: Luca Fancellu <Luca.Fancellu@xxxxxxx>, "michal.orzel@xxxxxxx" <michal.orzel@xxxxxxx>, Julien Grall <jgrall@xxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
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- Thread-topic: [PATCH 6/7] xen/arm: mm: Add missing ISB in xen_pt_update()
Hi Julien,
> -----Original Message-----
> Subject: [PATCH 6/7] xen/arm: mm: Add missing ISB in xen_pt_update()
>
> From: Julien Grall <jgrall@xxxxxxxxxx>
>
> Per the Arm Arm, (Armv7 DDI406C.d A3.8.3 and Armv8 DDI 0487J.a B2.3.12):
>
> "The DMB and DSB memory barriers affect reads and writes to the memory
> system generated by load/store instructions and data or unified cache
> maintenance operations being executed by the processor. Instruction
> fetches or accesses caused by a hardware translation table access are
> not explicit accesses."
>
> Note that second sentence is not part of the newer Armv8 spec. But the
> interpretation is not much different.
>
> The updated entry will not be used until xen_pt_update() completes.
> So rather than adding the ISB after write_pte() in create_xen_table()
> and xen_pt-update_entry(), add it in xen_pt_update().
>
> Also document the reasoning of the deferral after each write_pte() calls.
>
> Fixes: 07d11f63d03e ("xen/arm: mm: Avoid flushing the TLBs when mapping
> are inserted")
> Signed-off-by: Julien Grall <jgrall@xxxxxxxxxx>
Reviewed-by: Henry Wang <Henry.Wang@xxxxxxx>
I've also tested this patch on top of today's staging by our internal CI, and
this
patch looks good, so:
Tested-by: Henry Wang <Henry.Wang@xxxxxxx>
Kind regards,
Henry
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