[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v1 17/23] xen/pt: add Resizable BAR PCIe Extended Capability descriptor and sizing
Unlike other PCIe Extended Capabilities, we currently cannot allow attempts to use Resizable BAR Capability. Without specifically handling BAR resizing we're likely end up with corrupted MMIO hole layout if guest OS will attempt to use this feature. Actually, recent Windows versions started to understand and use the Resizable BAR Capability (see [1]). For now, we need to hide the Resizable BAR Capability from guest OS until BAR resizing emulation support will be implemented in Xen. This support is a pretty much mandatory todo-feature as the effect of writing to Resizable BAR control registers can be considered similar to reprogramming normal BAR registers -- i.e. this needs to be handled explicitly, resulting in corresponding MMIO BAR range(s) remapping. Until then, we mark the Resizable BAR Capability as XEN_PT_GRP_TYPE_HARDWIRED. Signed-off-by: Alexey Gerasimenko <x1917x@xxxxxxxxx> Signed-off-by: Joel Upham <jupham125@xxxxxxxxx> --- hw/xen/xen_pt_config_init.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 1fba0b9d6c..c5157ee3ee 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -2093,6 +2093,27 @@ static int xen_pt_ext_cap_pmux_size_init(XenPCIPassthroughState *s, return ret; } +/* get Resizable BAR Extended Capability register group size */ +static int xen_pt_ext_cap_rebar_size_init(XenPCIPassthroughState *s, + const XenPTRegGroupInfo *grp_reg, + uint32_t base_offset, + uint32_t *size) +{ + uint32_t rebar_ctl = 0; + uint32_t num_entries; + + int ret = xen_host_pci_get_long(&s->real_device, + base_offset + PCI_REBAR_CTRL, + &rebar_ctl); + num_entries = + (rebar_ctl & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT; + + *size = num_entries*8 + 4; + + log_pcie_extended_cap(s, "Resizable BAR", base_offset, *size); + return ret; +} + static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { /* Header Type0 reg group */ { @@ -2424,6 +2445,13 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { .size_init = xen_pt_ext_cap_dpc_size_init, .emu_regs = xen_pt_ext_cap_emu_reg_dummy, }, + /* Resizable BAR Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_REBAR), + .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, + .grp_size = 0xFF, + .size_init = xen_pt_ext_cap_rebar_size_init, + }, { .grp_size = 0, }, -- 2.34.1
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