[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [XEN PATCH v2 12/13] xen/x86: fix violations of MISRA C:2012 Rule 7.2


  • To: Simone Ballarin <simone.ballarin@xxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Thu, 6 Jul 2023 18:22:40 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4VUaRakA8WXAnt74HRa63Lz7G4ULWu80U3CpXtW1wTI=; b=nMMKheQggf4TYJkXoiPdxyGYaKXIcxldWORAv9Uv08T3UjmdNVnWdzMXKKyPs0jfZyBw3PmxT1PkfP4Wt6wm1GQ2td46Ex+bXLBKcgcwEv9mZ8se8DwOzqM+LgYEC43TQhgH2Hg0jbHod0bIfpR4S4WMvaS5aePBn6TJjb50YA8fNmTFbtMteXqBxKeLiUIrkL0GivjLyQbDdH0w1onqZwO6oUpvF14JZkxGj8+F0pJ39/VPZ9AkFUyLVfYxAUtwzz40dP0BFcx6nPgE9yiPif9KLj5zv5AmBoUEyz1EF9UmqhgUpKqrg9XJ4x/siuJfnBW2BI4Y/RaGFVrZqDBwcA==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nRwIwElOGE3UXmFigUas2qYOjerWOW3zfaf9WJiRUQLkRf7v++WN4w4l+N30dAMZHZXU57wx2YryND8o5zTQLxEFgtx9LPBLozKej8xWgRfJyLdY2acnkfVTVxMmxJXR12vu1Qj5cGTBa/I5NQYshRV7OqDIdCgV3e41POygSXJJLaAiPljtIG2CI+CmFjrgcItHJRcsiLY62JxAmMIXsMPJdI81tMrAjVblmH+7PS16ePIkcX/HVqMQlmig70omKEDUMoi1rNULW3b+8Sxy1tN6FIDzHHYf8AmzP3CzW4aaz6IvSF7/Ijp757FdtObdh8YkbnHgFFn+YLbGiHNoxw==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
  • Cc: consulting@xxxxxxxxxxx, Gianluca Luparini <gianluca.luparini@xxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Paul Durrant <paul@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Xenia Ragiadakou <Xenia.Ragiadakou@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Thu, 06 Jul 2023 16:22:50 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 06.07.2023 18:08, Simone Ballarin wrote:
> Il giorno gio 6 lug 2023 alle ore 10:26 Jan Beulich <jbeulich@xxxxxxxx> ha
> scritto:
> 
>> On 05.07.2023 17:26, Simone Ballarin wrote:
>>> --- a/xen/arch/x86/apic.c
>>> +++ b/xen/arch/x86/apic.c
>>> @@ -1211,7 +1211,7 @@ static void __init calibrate_APIC_clock(void)
>>>       * Setup the APIC counter to maximum. There is no way the lapic
>>>       * can underflow in the 100ms detection time frame.
>>>       */
>>> -    __setup_APIC_LVTT(0xffffffff);
>>> +    __setup_APIC_LVTT(0xffffffffU);
>>
>> While making the change less mechanical, we want to consider to switch
>> to ~0 in this and similar cases.
>>
> 
> Changing ~0U is more than not mechanical: it is possibly dangerous.
> The resulting value could be different depending on the architecture,
> I prefer to not make such kind of changes in a MISRA-related patch.

What do you mean by "depending on the architecture", when this is
x86-only code _and_ you can check what type parameter the called
function has?

Jan



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.