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[PATCH v3 0/4] x86/ioapic: fix edge triggered interrupt migration
- To: xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Date: Wed, 26 Jul 2023 14:55:04 +0200
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- Cc: Roger Pau Monne <roger.pau@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>, Paul Durrant <paul@xxxxxxx>
- Delivery-date: Wed, 26 Jul 2023 12:55:38 +0000
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- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hello,
Following series attempts to solve the issue with IO-APIC edge triggered
interrupts seeing an inconsistent IRTE when injected while being
migrated.
It's been simplified a bit from the original RFC, and does make the
logic in the IOMMU RTE update handlers cleaner, as those get passed the
full RTE.
When not using interrupt remapping the logic is left as-is. One further
change would be to mask edge triggered interrupts, as destination and
vector cannot be changed atomically when dealing with plain IO-APIC
RTEs.
The previously final patch to switch AMD IOMMU to use atomic RTE updates
has been drop pending feedback from AMD on whether that approach is
suitable.
Thanks, Roger.
Roger Pau Monne (4):
x86/ioapic: add a raw field to RTE struct
x86/ioapic: RTE modifications must use ioapic_write_entry
iommu/vtd: rename io_apic_read_remap_rte() local variable
x86/iommu: pass full IO-APIC RTE for remapping table update
xen/arch/x86/include/asm/io_apic.h | 65 ++++++-----
xen/arch/x86/include/asm/iommu.h | 3 +-
xen/arch/x86/io_apic.c | 46 ++++----
xen/drivers/passthrough/amd/iommu.h | 2 +-
xen/drivers/passthrough/amd/iommu_intr.c | 106 ++---------------
xen/drivers/passthrough/vtd/extern.h | 2 +-
xen/drivers/passthrough/vtd/intremap.c | 140 +++++++++++------------
xen/drivers/passthrough/x86/iommu.c | 4 +-
xen/include/xen/iommu.h | 3 +-
9 files changed, 142 insertions(+), 229 deletions(-)
--
2.41.0
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