Re: [PATCH v8 2/6] xen/riscv: introduce <asm/bug.h>

[Alistair Francis <alistair23@xxxxxxxxx>]

On Fri, Aug 11, 2023 at 10:33 AM Oleksii Kurochko
<oleksii.kurochko@xxxxxxxxx> wrote:
>
> Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>

Reviewed-by: Alistair Francis <alistair.francis@xxxxxxx>

Alistair

> ---
> Changes in V8:
>  - new patch. It was introduced instead of dummy asm/bug.h introduction.
> ---
>  xen/arch/riscv/include/asm/bug.h | 37 ++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
>  create mode 100644 xen/arch/riscv/include/asm/bug.h
>
> diff --git a/xen/arch/riscv/include/asm/bug.h 
> b/xen/arch/riscv/include/asm/bug.h
> new file mode 100644
> index 0000000000..f5ff96140f
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/bug.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2012 Regents of the University of California
> + * Copyright (C) 2021-2023 Vates
> + *
> + */
> +#ifndef _ASM_RISCV_BUG_H
> +#define _ASM_RISCV_BUG_H
> +
> +#ifndef __ASSEMBLY__
> +
> +#define BUG_INSTR "ebreak"
> +
> +/*
> + * The base instruction set has a fixed length of 32-bit naturally aligned
> + * instructions.
> + *
> + * There are extensions of variable length ( where each instruction can be
> + * any number of 16-bit parcels in length ).
> + *
> + * Compressed ISA is used now where the instruction length is 16 bit  and
> + * 'ebreak' instruction, in this case, can be either 16 or 32 bit (
> + * depending on if compressed ISA is used or not )
> + */
> +#define INSN_LENGTH_MASK        _UL(0x3)
> +#define INSN_LENGTH_32          _UL(0x3)
> +
> +#define BUG_INSN_32             _UL(0x00100073) /* ebreak */
> +#define BUG_INSN_16             _UL(0x9002)     /* c.ebreak */
> +#define COMPRESSED_INSN_MASK    _UL(0xffff)
> +
> +#define GET_INSN_LENGTH(insn)                               \
> +    (((insn) & INSN_LENGTH_MASK) == INSN_LENGTH_32 ? 4 : 2) \
> +
> +#endif /* !__ASSEMBLY__ */
> +
> +#endif /* _ASM_RISCV_BUG_H */
> --
> 2.41.0
>
>