[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v2 6/8] x86/hvm: Add comments about #DB exception behavior to {svm,vmx}_inject_event()
From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Extracted comments only, and then s/from emulation/from monitor/; originally "x86/hvm: RFC - PROBABLY BROKEN - Defer all debugging/monitor actions to {svm,vmx}_inject_event()" Signed-off-by: Jinoh Kang <jinoh.kang.kr@xxxxxxxxx> --- CC: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> CC: Jan Beulich <JBeulich@xxxxxxxx> CC: Wei Liu <wl@xxxxxxx> CC: Roger Pau Monné <roger.pau@xxxxxxxxxx> CC: Jun Nakajima <jun.nakajima@xxxxxxxxx> CC: Kevin Tian <kevin.tian@xxxxxxxxx> v1 -> v2: new patch --- xen/arch/x86/hvm/svm/svm.c | 9 +++++++++ xen/arch/x86/hvm/vmx/vmx.c | 7 +++++++ 2 files changed, 16 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 6f3e6b3512..7bb572e72b 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1328,6 +1328,15 @@ static void cf_check svm_inject_event(const struct x86_event *event) switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) { case X86_EXC_DB: + /* + * On AMD hardware, a #DB exception: + * 1) Merges new status bits into %dr6 + * 2) Clears %dr7.gd and MSR_DEBUGCTL.{LBR,BTF} + * + * Item 1 is done by hardware before a #DB intercepted vmexit, but we + * may end up here from monitor so have to repeat it ourselves. + * Item 2 is done by hardware when injecting a #DB exception. + */ __restore_debug_registers(vmcb, curr); vmcb_set_dr6(vmcb, vmcb_get_dr6(vmcb) | _event.pending_dbg); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 4e20fca43e..b35278992a 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2022,6 +2022,13 @@ static void cf_check vmx_inject_event(const struct x86_event *event) switch ( _event.vector | -(_event.type == X86_EVENTTYPE_SW_INTERRUPT) ) { case X86_EXC_DB: + /* + * On Intel hardware, a #DB exception: + * 1) Merges new status bits into %dr6 + * 2) Clears %dr7.gd and MSR_DEBUGCTL.LBR + * + * All actions are left up to the hypervisor to perform. + */ __restore_debug_registers(curr); write_debugreg(6, read_debugreg(6) | event->pending_dbg); -- 2.41.0
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