Re: [PATCH 8/8] x86/spec-ctrl: Mitigate the Zen1 DIV leakge

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 13/09/2023 9:27 pm, Andrew Cooper wrote:
> @@ -955,6 +960,40 @@ static void __init srso_calculations(bool hw_smt_enabled)
>          setup_force_cpu_cap(X86_FEATURE_SRSO_NO);
>  }
>  
> +/*
> + * Div leakage is specific to the AMD Zen1 microarchitecure.  Use STIBP as a
> + * heuristic to select between Zen1 and Zen2 uarches.
> + */
> +static bool __init has_div_vuln(void)
> +{
> +    if ( !(boot_cpu_data.x86_vendor &
> +           (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
> +        return false;
> +
> +    if ( (boot_cpu_data.x86 != 0x17 && boot_cpu_data.x86 != 0x18) ||
> +         !boot_cpu_has(X86_FEATURE_AMD_STIBP) )
> +        return false;

Bah - this serves me right for positing before waiting for CI to check
that Naples picks the right default.  The STIBP check is backwards and
will mix up Zen1/2.

I'm going to create real is_zen{1,2}_uarch() helpers in amd.h to avoid
opencoding this heuristic yet again.  I highly doubt this will be the
final time we need it.

~Andrew