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Re: [PATCH 2/5] x86: Introduce x86_merge_dr6()
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Fri, 15 Sep 2023 09:42:19 +0200
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Jinoh Kang <jinoh.kang.kr@xxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Fri, 15 Sep 2023 07:42:28 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 14.09.2023 20:03, Andrew Cooper wrote:
> On 14/09/2023 3:53 pm, Jan Beulich wrote:
>> On 13.09.2023 01:21, Andrew Cooper wrote:
>>> The current logic used to update %dr6 when injecting #DB is buggy. The
>>> architectural behaviour is to overwrite B{0..3} and accumulate all other
>>> bits.
>> While I consider this behavior plausible, forever since the introduction of
>> debug registers in i386 I have been missing a description in the manuals of
>> how %dr6 updating works. Can you point me at where the above is actually
>> spelled out?
>
> The documentation is very poor. The comment in the code is based on my
> conversations with architects.
Especially in such a case, can you please make very explicit in the
description what the origin of the information is? That way it's
simply impossible for anyone to review properly without having had
the same conversations.
Jan
> APM Vol2 13.1.1.3 Debug-Status Register (DR6) says
>
> "Bits 15:13 of the DR6 register are not cleared by the processor and
> must be cleared by software after the contents have been read."
>
> although this is buggy given the addition of BLD in the latest
> revision. I've asked AMD to correct it.
>
>
> SDM Vol3 18.2.3 Debug Status Register (DR6) says
>
> "Certain debug exceptions may clear bits 0-3. The remaining contents of
> the DR6 register are never cleared by the processor."
>
> ~Andrew
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