[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2] ARM: GICv3 ITS: flush caches for newly allocated ITT
- To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Date: Fri, 22 Sep 2023 22:27:15 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=epam.com; dmarc=pass action=none header.from=epam.com; dkim=pass header.d=epam.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6VSbBxXyIlHorQ3Rjke6VWSGP5oamwT8jeSrL/OFptk=; b=RBHdZ+TPPdMV+U00SwhLV0HRWbm6VtUMSFXRluzllG44u3+noxHV+Pb5Oy6HzDup1d71wikloKjOx9M3hO0TZiZxuXqMMjPZi+XhdMeMwPFJcYbAj7dTMhna/oIWXEdI5Fyb86s8c7OnhA3ME0Eqo+LzGSDG9m9q8u++576w61WOZxvEY9uTvLUlc/FyzO2l7nUV5gRMfcwIS1mSnUPy5fyG7e3KJFOo1Ua7fBZGMq0z55AX91VwyNsfAz0i1VJbmwiSJeiHNAGABwJUv0NfBm8t8zgtEj0dU7dem9pIJ2qUWRaRF3zspU0LbsdSaWmeEBMDBqRzFnd/Mc5zxwTG/w==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jULt63a5JHic0NVKsl3jEfoLv6h5XRUy7t4Tn1swxOflYqr0zUMa9QWPmhAJI8/ZILV9MvP4ROgy+BkNs3vOwDJ1tvIGm7jM6td29s1qgvP5ApwH8rZYeaCD+seS5cizzWu348fvOTb6Sw3YwOnaxiniDWdJlJj8gSHuj75G7QpIO8mKW1Fo1GV8C3bE5Z/adGh2Z2tsgkGiu3bLjC/taJ6GmVOBdWFLL7INGWVB3gh04gFcnpOioDNRKNfbRMY/qh7VI2jFkR16HhH+jhCUOSdCUj7M1ab1jcA6ul1OqRhHSUEDw+G9NCqUZcT7jM/01eO7rAE6/lAWtgoca4KpdQ==
- Cc: Stewart Hildebrand <stewart.hildebrand@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Fri, 22 Sep 2023 22:27:38 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHZ7aPwbLIfEqCF/k2PKMU6gFIgCg==
- Thread-topic: [PATCH v2] ARM: GICv3 ITS: flush caches for newly allocated ITT
ITS manages Device Tables and Interrupt Translation Tables on its own,
so generally we are not interested in maintaining any coherence with
CPU's view of those memory regions, except one case: ITS requires that
Interrupt Translation Tables should be initialized with
zeroes. Existing code already does this, but it does not cleans
caches afterwards. This means that ITS may see un-initialized ITT and
CPU can overwrite portions of ITT later, when it finally decides to
flush caches. Visible effect of this issue that there are not
interrupts delivered from a device.
Fix this by calling clean_and_invalidate_dcache_va_range() for newly
allocated ITT.
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
---
Changes since v1:
- Use clean_and_invalidate_dcache_va_range() instead of
clean_dcache_va_range()
- Do this unconditionally
- Do not rename HOST_ITS_FLUSH_CMD_QUEUE into HOST_ITS_FLUSH_BUFFERS
---
xen/arch/arm/gic-v3-its.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
index 3aa4edda10..8afcd9783b 100644
--- a/xen/arch/arm/gic-v3-its.c
+++ b/xen/arch/arm/gic-v3-its.c
@@ -685,6 +685,9 @@ int gicv3_its_map_guest_device(struct domain *d,
if ( !itt_addr )
goto out_unlock;
+ clean_and_invalidate_dcache_va_range(itt_addr,
+ nr_events * hw_its->itte_size);
+
dev = xzalloc(struct its_device);
if ( !dev )
goto out_unlock;
--
2.42.0
|
