[for-4.18][PATCH v2] x86/amd: Address AMD erratum #1485

[Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>]

Fix adapted off Linux's mailing list:
  
https://lore.kernel.org/lkml/D99589F4-BC5D-430B-87B2-72C20370CF57@xxxxxxxxxxxxx/T/#u

Signed-off-by: Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>
Release-acked-by: Henry Wang <Henry.Wang@xxxxxxx>
---
v2:
  * Removed v1/patch1, as it proved to be contentious
    * Also changed is_zen[34]_uarch() into a heuristic check only
  * Streamlined comments and commit message

---
 xen/arch/x86/cpu/amd.c               | 8 ++++++++
 xen/arch/x86/include/asm/amd.h       | 5 +++++
 xen/arch/x86/include/asm/msr-index.h | 1 +
 3 files changed, 14 insertions(+)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 4f27187f92..085c4772d7 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1167,6 +1167,14 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
        if (c->x86 == 0x10)
                __clear_bit(X86_FEATURE_MONITOR, c->x86_capability);
 
+       /* Fix for AMD erratum #1485 */
+       if (!cpu_has_hypervisor && c->x86 == 0x19 && is_zen4_uarch()) {
+               rdmsrl(MSR_AMD64_BP_CFG, value);
+               #define ZEN4_BP_CFG_SHARED_BTB_FIX (1ull << 5)
+               wrmsrl(MSR_AMD64_BP_CFG,
+                      value | ZEN4_BP_CFG_SHARED_BTB_FIX);
+       }
+
        if (!cpu_has_amd_erratum(c, AMD_ERRATUM_121))
                opt_allow_unsafe = 1;
        else if (opt_allow_unsafe < 0)
diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h
index d862cb7972..0700827561 100644
--- a/xen/arch/x86/include/asm/amd.h
+++ b/xen/arch/x86/include/asm/amd.h
@@ -145,11 +145,16 @@
  * Hygon (Fam18h) but without simple model number rules.  Instead, use STIBP
  * as a heuristic that distinguishes the two.
  *
+ * For Zen3 and Zen4 (Fam19h) the heuristic is the presence of AutoIBRS, as
+ * it's Zen4-specific.
+ *
  * The caller is required to perform the appropriate vendor/family checks
  * first.
  */
 #define is_zen1_uarch() (!boot_cpu_has(X86_FEATURE_AMD_STIBP))
 #define is_zen2_uarch()   boot_cpu_has(X86_FEATURE_AMD_STIBP)
+#define is_zen3_uarch() (!boot_cpu_has(X86_FEATURE_AUTO_IBRS))
+#define is_zen4_uarch()   boot_cpu_has(X86_FEATURE_AUTO_IBRS)
 
 struct cpuinfo_x86;
 int cpu_has_amd_erratum(const struct cpuinfo_x86 *, int, ...);
diff --git a/xen/arch/x86/include/asm/msr-index.h 
b/xen/arch/x86/include/asm/msr-index.h
index 11ffed543a..7b3490bfb1 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -403,6 +403,7 @@
 #define MSR_AMD64_DE_CFG               0xc0011029
 #define AMD64_DE_CFG_LFENCE_SERIALISE  (_AC(1, ULL) << 1)
 #define MSR_AMD64_EX_CFG               0xc001102c
+#define MSR_AMD64_BP_CFG               0xc001102e
 #define MSR_AMD64_DE_CFG2              0xc00110e3
 
 #define MSR_AMD64_DR0_ADDRESS_MASK     0xc0011027
-- 
2.34.1