[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [XEN PATCH 4/4] xen: address violations of MISRA C:2012 Rule 13.1


  • To: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Simone Ballarin <simone.ballarin@xxxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Thu, 19 Oct 2023 11:35:18 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Pv+kPGT/Jmzqr4TLzPAXHp6uYmmXls4E8Q7d8Tt1sjc=; b=blgRzAHYm9OsK6CsL9j6SL5RDkos/m4yZ5+0qB1WUNq/I+GJaYLRdtTBQkAhblGqmjNRwC+3rDmBUp2THGI42fmAQ8VVCXleAgjR2tBb9xYVYbJ+qNH+cely6/YhdgC++kRnXcfphhdjSHZUM99wOzvoG6pSr2atNo04ig194MXfh2rhYI+tRYZLeDJhtFgFspcWOqvNultaajgYkQFsv8+CXaak0gSnTxvYS8fDFIaLfZ7gkr9YV2UCd/OMxQYJW83/fwLu7CrGCD18bp0kvXLoVyohAN9Tje4YApF9h1qZe/xydjvuVn+BkadycYSpBkICzMBElWuU4MwGLXH7Zw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=REtYofH8Mnxq7IqBubSzbgdAM78iLBfJ1BqUkcY0HYGcwRbBhZU+ZP487LKLS2Ep0L5ND63TlByziuB+m5DNjuDrtL8mLpAy8ZttLovWFM3nRZB1YPqXnO0pVBc2NGPTHeR+LZcZ0J9bQAgHkiDPSm8lpjgrSGsCxt6QASUrHggl5X7HAp9zs4vKrki1bzCyR9hPesDtwmQpzlzmfO52AVKI2zCG9nyMdE47LeK8/AMkflwgeZVfpX1IbHc9HL+H/TJzGZ/tSioWh1dOBT3FVQ5OJy4qVnotr20rv7Zg8Im4Z+JJu+bS22z1uzGNHIJMViNbh6/NWVAkHogqfp7S4A==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
  • Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx, consulting@xxxxxxxxxxx, George Dunlap <george.dunlap@xxxxxxxxxx>, Dario Faggioli <dfaggioli@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Wei Liu <wl@xxxxxxx>
  • Delivery-date: Thu, 19 Oct 2023 09:35:26 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 19.10.2023 03:06, Stefano Stabellini wrote:
> On Wed, 18 Oct 2023, Simone Ballarin wrote:
>> --- a/xen/common/sched/core.c
>> +++ b/xen/common/sched/core.c
>> @@ -1504,6 +1504,8 @@ long vcpu_yield(void)
>>  {
>>      struct vcpu * v=current;
>>      spinlock_t *lock;
>> +    domid_t domain_id;
>> +    int vcpu_id;
>>  
>>      rcu_read_lock(&sched_res_rculock);
>>  
>> @@ -1515,7 +1517,9 @@ long vcpu_yield(void)
>>  
>>      SCHED_STAT_CRANK(vcpu_yield);
>>  
>> -    TRACE_2D(TRC_SCHED_YIELD, current->domain->domain_id, current->vcpu_id);
>> +    domain_id = current->domain->domain_id;
>> +    vcpu_id = current->vcpu_id;
>> +    TRACE_2D(TRC_SCHED_YIELD, domain_id, vcpu_id);
> 
> Also here it looks like accessing the current pointer is considered a
> side effect. Why? This is a just a global variable that is only accessed
> for reading.

Not exactly. It's a per-CPU variable access on Arm, but involves a
function call on x86. Still that function call has no other side
effects, but I guess Misra wouldn't honor this.

I'm afraid though that the suggested change violates rule 2.2, as
the two new assignments are dead code when !CONFIG_TRACEBUFFER.

Jan



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.