Re: QEMU features useful for Xen development?

[Ayan Kumar Halder <ayankuma@xxxxxxx>]

Hi Alex,

On 20/10/2023 16:15, Alex Bennée wrote:
> Ayan Kumar Halder <ayankuma@xxxxxxx> writes:
>
> > Hi Peter/Alex,
> >
> > Appreciate your help. :)
> >
> > On 31/08/2023 11:03, Peter Maydell wrote:
> > > CAUTION: This message has originated from an External Source. Please
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> > >
> > >
> > > On Thu, 31 Aug 2023 at 10:53, Alex Bennée <alex.bennee@xxxxxxxxxx> wrote:
> > > > Peter Maydell <peter.maydell@xxxxxxxxxx> writes:
> > > >
> > > > > On Thu, 31 Aug 2023 at 01:57, Stefano Stabellini <sstabellini@xxxxxxxxxx> wrote:
> > > > > > As Xen is gaining R52 and R82 support, it would be great to be able to
> > > > > > use QEMU for development and testing there as well, but I don't think
> > > > > > QEMU can emulate EL2 properly for the Cortex-R architecture. We would
> > > > > > need EL2 support in the GIC/timer for R52/R82 as well.
> > > > > We do actually have a Cortex-R52 model which at least in theory
> > > > > should include EL2 support, though as usual with newer QEMU
> > > > > stuff it quite likely has lurking bugs; I'm not sure how much
> > > > > testing it's had. Also there is currently no board model which
> > > > > will work with the Cortex-R52 so it's a bit tricky to use in practice.
> > > > > (What sort of board model would Xen want to use it with?)
> > > > We already model a bunch of the mps2/mps3 images so I'm assuming adding
> > > > the mps3-an536 would be a fairly simple step to do (mps2tz.c is mostly
> > > > tweaking config values). The question is would it be a useful target for
> > > > Xen?
> > > All our MPS2/MPS3 boards are M-profile. That means we have the
> > > device models for all the interesting devices on the board, but
> > > it would be simpler to write the an536 board model separately.
> > > (In particular, the M-profile boards are wrappers around an
> > > "ARMSSE" sort-of-like-an-SoC component; there's no equivalent
> > > for the Cortex-R52.)
> > >
> > > >     https://developer.arm.com/documentation/dai0536/latest/
> > Yes, it will be helpful if Qemu can model this board. We have a
> > downstream port of Xen on R52 (upstreaming is in progress).
> >
> > So, we can test the Qemu model with Xen.
> >
> > Also if all works fine, we might consider adding this to the upstream
> > Xen CI docker.
> We wrote up whats required on our JIRA:
>
>    https://linaro.atlassian.net/browse/QEMU-598
>
> Given we have most of the bits already it shouldn't take long to build a
> model for it. However I want to draw every ones attention to the notes:
>
>    The real FPGA image does not have a global monitor that can support
>    LDREX/STREX between the two CPUs for accesses in the DDR4 RAM or BRAM.
>    This means that effectively guest software will only be able to use
>    one CPU (the local monitor within the CPU works fine). This
>    restriction won’t apply to the QEMU model, but is important to be
>    aware of if you’re writing guest software on the QEMU model that you
>    also want to be able to run on the FPGA board.
>
> However if that meets the requirements for Xen testing and no one tries
> to run SMP loads on real HW then I can try and find space on our roadmap
> to do it (rough guess 9.1 or 9.2?).
Yes, this meets the requirements for Xen testing.

It will be great to use Qemu for Xen testing.

Please keep me posted on this feature as I am plumbing the R52 bits in 
upstream Xen.
- Ayan

>