[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [RFC PATCH 11/22] x86/PMUv2: freeze support in IA32_DEBUGCTL
From: Edwin Török <edvin.torok@xxxxxxxxxx> This is not yet exposed by HVM policies, but PMU version 2 requires that if PDCM is supported in CPUID then these 2 bits would work. Signed-off-by: Edwin Török <edvin.torok@xxxxxxxxxx> --- xen/arch/x86/hvm/vmx/vmx.c | 4 ++++ xen/arch/x86/include/asm/msr-index.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 1510e980dd..f1f8a9afa2 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3601,6 +3601,10 @@ static int cf_check vmx_msr_write_intercept( IA32_DEBUGCTLMSR_BTS_OFF_USR); } + if (cp->basic.pmu_version >= 2 && cpu_has(¤t_cpu_data, X86_FEATURE_PDCM)) { + rsvd &= ~(IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI | IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI); + } + if ( cp->feat.rtm ) rsvd &= ~IA32_DEBUGCTLMSR_RTM; diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 8a881a8a6f..0dfb5b499f 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -305,7 +305,9 @@ #define IA32_DEBUGCTLMSR_BTINT (1<<8) /* Branch Trace Interrupt */ #define IA32_DEBUGCTLMSR_BTS_OFF_OS (1<<9) /* BTS off if CPL 0 */ #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */ -#define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ +#define IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1<<11) /* LBR stack frozen on PMI */ +#define IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1<<12) /* Global counter control ENABLE bit frozen on PMI */ +#define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db #define MSR_IA32_LASTBRANCHTOIP 0x000001dc -- 2.41.0
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