[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v7 1/2] xen/vpci: header: status register handler
On Fri, Nov 17, 2023 at 02:23:42PM +0100, Jan Beulich wrote: > On 17.11.2023 13:40, Roger Pau Monné wrote: > > On Wed, Sep 13, 2023 at 10:35:46AM -0400, Stewart Hildebrand wrote: > >> --- a/xen/drivers/vpci/vpci.c > >> +++ b/xen/drivers/vpci/vpci.c > >> @@ -29,6 +29,9 @@ struct vpci_register { > >> unsigned int offset; > >> void *private; > >> struct list_head node; > >> + uint32_t rsvdz_mask; > >> + uint32_t ro_mask; > >> + uint32_t rw1c_mask; > > > > I understand that we need the rw1c_mask in order to properly merge > > values when doing partial writes, but the other fields I'm not sure we > > do need them. RO bits don't care about what's written to them, and > > RsvdZ are always read as 0 and written as 0, so the mask shouldn't > > affect the merging. > > What some version of the spec says is r/o or reserved may be different > in another. Also iirc devices may (wrongly?) implement r/o bits as r/w. > When presenting a virtual view of devices to guests, in this regard I > think we want (or even need) to enforce our view of the world. That needs to be part of the commit message then. Ideally we would also want to do a swept of all registers we currently implement, in order to check for ro or rsvdz bits and properly enforce them. Thanks, Roger.
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