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Re: [PATCH v2] x86/cpuid: enumerate and expose PREFETCHIT{0,1}


  • To: Jan Beulich <jbeulich@xxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 22 Nov 2023 12:25:53 +0000
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  • Cc: Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Delivery-date: Wed, 22 Nov 2023 12:26:04 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 22/11/2023 7:43 am, Jan Beulich wrote:
> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -274,7 +274,7 @@ def crunch_numbers(state):
>          # superpages, PCID and PKU are only available in 4 level paging.
>          # NO_LMSL indicates the absense of Long Mode Segment Limits, which
>          # have been dropped in hardware.
> -        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL],
> +        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, PREFETCHI],

I know this is what the ISE says, but I'm not sure it's a legitimate
dependency.

It is an implementation detail that Intel depend on a RIP-relative
address, but there are no architectural reason why other implementations
couldn't make this work in 32bit too.

The worst that happens without this dependency is that 32bit-only VMs
see a hint bit about certain NOPs having uarch side effects, which
they'll ignore for other reasons.

So I recommend dropping the dependency.  If you're happy, then
Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

~Andrew



 


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