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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v3 2/7] x86/p2m: move and rename paging_max_paddr_bits()
The function also supports non-paging domains, and hence it being placed in
p2m.h and named with the paging_ prefix is misleading.
Move to x86 domain.c and rename to domain_max_paddr_bits(). Moving to a
different header is non trivial, as the function depends on helpers declared in
p2m.h. There's no performance reason for the function being inline.
No functional change intended.
Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
Changes since v2:
- New in this version.
---
xen/arch/x86/cpu-policy.c | 2 +-
xen/arch/x86/domain.c | 21 +++++++++++++++++++++
xen/arch/x86/include/asm/domain.h | 3 +++
xen/arch/x86/include/asm/paging.h | 22 ----------------------
4 files changed, 25 insertions(+), 23 deletions(-)
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 423932bc13d6..76efb050edf7 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -864,7 +864,7 @@ void recalculate_cpuid_policy(struct domain *d)
p->extd.maxphysaddr = min(p->extd.maxphysaddr, max->extd.maxphysaddr);
p->extd.maxphysaddr = min_t(uint8_t, p->extd.maxphysaddr,
- paging_max_paddr_bits(d));
+ domain_max_paddr_bits(d));
p->extd.maxphysaddr = max_t(uint8_t, p->extd.maxphysaddr,
(p->basic.pae || p->basic.pse36) ? 36 : 32);
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 3712e36df930..8a31d18f6967 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -2552,6 +2552,27 @@ static int __init cf_check init_vcpu_kick_softirq(void)
}
__initcall(init_vcpu_kick_softirq);
+unsigned int domain_max_paddr_bits(const struct domain *d)
+{
+ unsigned int bits = paging_mode_hap(d) ? hap_paddr_bits : paddr_bits;
+
+ if ( paging_mode_external(d) )
+ {
+ if ( !IS_ENABLED(CONFIG_BIGMEM) && paging_mode_shadow(d) )
+ {
+ /* Shadowed superpages store GFNs in 32-bit page_info fields. */
+ bits = min(bits, 32U + PAGE_SHIFT);
+ }
+ else
+ {
+ /* Both p2m-ept and p2m-pt only support 4-level page tables. */
+ bits = min(bits, 48U);
+ }
+ }
+
+ return bits;
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/x86/include/asm/domain.h
b/xen/arch/x86/include/asm/domain.h
index 4b6b7ceab1ed..622d22bef255 100644
--- a/xen/arch/x86/include/asm/domain.h
+++ b/xen/arch/x86/include/asm/domain.h
@@ -777,6 +777,9 @@ static inline void pv_inject_sw_interrupt(unsigned int
vector)
struct arch_vcpu_io {
};
+/* Maxphysaddr supportable by the paging infrastructure. */
+unsigned int domain_max_paddr_bits(const struct domain *d);
+
#endif /* __ASM_DOMAIN_H__ */
/*
diff --git a/xen/arch/x86/include/asm/paging.h
b/xen/arch/x86/include/asm/paging.h
index 76162a9429ce..8a2a0af40874 100644
--- a/xen/arch/x86/include/asm/paging.h
+++ b/xen/arch/x86/include/asm/paging.h
@@ -336,28 +336,6 @@ static inline bool gfn_valid(const struct domain *d, gfn_t
gfn)
return !(gfn_x(gfn) >> (d->arch.cpuid->extd.maxphysaddr - PAGE_SHIFT));
}
-/* Maxphysaddr supportable by the paging infrastructure. */
-static always_inline unsigned int paging_max_paddr_bits(const struct domain *d)
-{
- unsigned int bits = paging_mode_hap(d) ? hap_paddr_bits : paddr_bits;
-
- if ( paging_mode_external(d) )
- {
- if ( !IS_ENABLED(CONFIG_BIGMEM) && paging_mode_shadow(d) )
- {
- /* Shadowed superpages store GFNs in 32-bit page_info fields. */
- bits = min(bits, 32U + PAGE_SHIFT);
- }
- else
- {
- /* Both p2m-ept and p2m-pt only support 4-level page tables. */
- bits = min(bits, 48U);
- }
- }
-
- return bits;
-}
-
#endif /* XEN_PAGING_H */
/*
--
2.43.0
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