[PATCH v2 3/3] xen/arm: Introduce "partial-emulation" xen command line option

[Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>]

This option is used to enable/disable partial emulation of registers at runtime.
While CONFIG_PARTIAL_EMULATION enables support for partial emulation at compile
time (ie adds code for partial emulation), this option may be enabled or
disabled by Yocto or other build systems.
However, customers can use scripts like Imagebuilder to generate uboot script
for booting Xen. These scripts can use "partial-emulation=true" to support this
at runtime.

This option is set to false by default so that customers are fully aware when
they enable partial emulation. They can also disable it without the need to
rebuild Xen.

Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
---
Changes from v1:-

1. New patch introduced in v2.

 docs/misc/xen-command-line.pandoc |  7 +++++++
 xen/arch/arm/arm64/vsysreg.c      |  5 ++++-
 xen/arch/arm/include/asm/regs.h   |  6 ++++++
 xen/arch/arm/traps.c              |  3 +++
 xen/arch/arm/vcpreg.c             | 17 +++++++++++------
 5 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc 
b/docs/misc/xen-command-line.pandoc
index 8e65f8bd18..dd2a76fb19 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -1949,6 +1949,13 @@ This option is ignored in **pv-shim** mode.
 
 > Default: `on`
 
+### partial-emulation (arm)
+> `= <boolean>`
+
+> Default: `false`
+
+Flag to enable or disable partial emulation of registers
+
 ### pci
     = List of [ serr=<bool>, perr=<bool> ]
 
diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index 0fa8716884..02497c9fef 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -192,7 +192,10 @@ void do_sysreg(struct cpu_user_regs *regs,
     case HSR_SYSREG_DBGDTR_EL0:
     /* DBGDTR[TR]X_EL0 share the same encoding */
     case HSR_SYSREG_DBGDTRTX_EL0:
-        return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0);
+        if ( opt_partial_emulation )
+            return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 0);
+        else
+            goto fail;
 #endif
 
     HSR_SYSREG_DBG_CASES(DBGBVR):
diff --git a/xen/arch/arm/include/asm/regs.h b/xen/arch/arm/include/asm/regs.h
index f998aedff5..b71fa20f91 100644
--- a/xen/arch/arm/include/asm/regs.h
+++ b/xen/arch/arm/include/asm/regs.h
@@ -13,6 +13,12 @@
 
 #define psr_mode(psr,m) (((psr) & PSR_MODE_MASK) == (m))
 
+/*
+ * opt_partial_emulation: If true, partial emulation for registers will be
+ * enabled.
+ */
+extern bool opt_partial_emulation;
+
 static inline bool regs_mode_is_32bit(const struct cpu_user_regs *regs)
 {
 #ifdef CONFIG_ARM_32
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index f5ab555b19..c8c00d2dd5 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -42,6 +42,9 @@
 #include <asm/vgic.h>
 #include <asm/vtimer.h>
 
+bool opt_partial_emulation = false;
+boolean_param("partial-emulation", opt_partial_emulation);
+
 /* The base of the stack must always be double-word aligned, which means
  * that both the kernel half of struct cpu_user_regs (which is pushed in
  * entry.S) and struct cpu_info (which lives at the bottom of a Xen
diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c
index 52a8732423..6bf417487a 100644
--- a/xen/arch/arm/vcpreg.c
+++ b/xen/arch/arm/vcpreg.c
@@ -578,12 +578,17 @@ void do_cp14_32(struct cpu_user_regs *regs, const union 
hsr hsr)
 #ifdef CONFIG_PARTIAL_EMULATION
     case HSR_CPREG32(DBGDTRTXINT):
     {
-        /*
-         * As DBGDSCRINT is emulated which is architecturally mapped to AArch64
-         * register MDCCSR_EL0. MDSCR_EL1 is not emulated. So DBGDTR[TR]XINT 
can
-         * only be accessed as EL0 level.
-         */
-        return handle_raz_wi(regs, regidx, cp32.read, hsr, 0);
+        if ( opt_partial_emulation )
+        {
+            /*
+             * As DBGDSCRINT is emulated which is architecturally mapped to
+             * AArch64 register MDCCSR_EL0. MDSCR_EL1 is not emulated. So
+             * DBGDTR[TR]XINT can only be accessed as EL0 level.
+             */
+            return handle_raz_wi(regs, regidx, cp32.read, hsr, 0);
+        }
+        else
+            goto fail;
     }
 #endif
 
-- 
2.25.1