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Re: [PATCH v2] x86/intel: ensure Global Performance Counter Control is setup correctly
- To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 11 Jan 2024 16:52:04 +0100
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Thu, 11 Jan 2024 15:52:11 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 11.01.2024 15:15, Roger Pau Monné wrote:
> On Thu, Jan 11, 2024 at 03:01:01PM +0100, Jan Beulich wrote:
>> On 11.01.2024 13:22, Roger Pau Monné wrote:
>>> Oh, indeed, can adjust on this same patch if that's OK (seeing as the
>>> issue was already there previous to my change).
>>
>> Well, I'm getting the impression that it was deliberate there, i.e. set
>> setting of the feature flag may want to remain thus constrained.
>
> Hm, I find it weird, but the original commit message doesn't help at
> all. Xen itself only uses PMC0, and I don't find any other
> justification in the current code to require at least 2 counters in
> order to expose arch performance monitoring to be present.
>
> Looking at the SDM vol3, the figures there only contain PMC0 and PMC1,
> so someone only reading that manual might assume there must always be
> 2 global PMCs?
That may have been the impression at the time. It may have been wrong
already back then, or ...
> (vol4 clarifies the that the number of global PMCs is variable).
... it may have been clarified in the SDM later on. My vague guess is
that the > 1 check was to skip what may have been "obviously buggy"
back at the time.
Jan
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