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Re: [XEN PATCH 02/10] xen/arm: address some violations of MISRA C Rule 20.7
- To: Nicola Vetrini <nicola.vetrini@xxxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 29 Feb 2024 17:34:53 +0100
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- Cc: sstabellini@xxxxxxxxxx, michal.orzel@xxxxxxx, xenia.ragiadakou@xxxxxxx, ayan.kumar.halder@xxxxxxx, consulting@xxxxxxxxxxx, andrew.cooper3@xxxxxxxxxx, roger.pau@xxxxxxxxxx, bertrand.marquis@xxxxxxx, julien@xxxxxxx, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Thu, 29 Feb 2024 16:34:59 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 29.02.2024 16:27, Nicola Vetrini wrote:
> --- a/xen/arch/arm/cpuerrata.c
> +++ b/xen/arch/arm/cpuerrata.c
> @@ -462,8 +462,8 @@ static bool has_ssbd_mitigation(const struct
> arm_cpu_capabilities *entry)
> #define MIDR_RANGE(model, min, max) \
> .matches = is_affected_midr_range, \
> .midr_model = model, \
> - .midr_range_min = min, \
> - .midr_range_max = max
> + .midr_range_min = (min), \
> + .midr_range_max = (max)
Why min and max, but not model?
> --- a/xen/arch/arm/include/asm/smccc.h
> +++ b/xen/arch/arm/include/asm/smccc.h
> @@ -122,7 +122,7 @@ struct arm_smccc_res {
> #define __constraint_read_7 __constraint_read_6, "r" (r7)
>
> #define __declare_arg_0(a0, res) \
> - struct arm_smccc_res *___res = res; \
> + struct arm_smccc_res *___res = (res); \
> register unsigned long r0 ASM_REG(0) = (uint32_t)a0; \
Why res but not a0?
> --- a/xen/arch/arm/include/asm/vgic-emul.h
> +++ b/xen/arch/arm/include/asm/vgic-emul.h
> @@ -6,11 +6,11 @@
> * a range of registers
> */
>
> -#define VREG32(reg) reg ... reg + 3
> -#define VREG64(reg) reg ... reg + 7
> +#define VREG32(reg) (reg) ... (reg) + 3
> +#define VREG64(reg) (reg) ... (reg) + 7
#define VREG32(reg) (reg) ... ((reg) + 3)
#define VREG64(reg) (reg) ... ((reg) + 7)
?
Jan
|
