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Re: [PATCH] hvmloader/PCI: skip huge BARs in certain calculations


  • To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Tue, 5 Mar 2024 10:56:45 +0100
  • Autocrypt: addr=jbeulich@xxxxxxxx; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL
  • Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Neowutran <xen@xxxxxxxxxxxxx>
  • Delivery-date: Tue, 05 Mar 2024 09:56:55 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 05.03.2024 10:25, Roger Pau Monné wrote:
> On Mon, Mar 04, 2024 at 02:25:45PM +0100, Jan Beulich wrote:
>> On 04.03.2024 11:02, Roger Pau Monné wrote:
>>>> --- a/tools/firmware/hvmloader/pci.c
>>>> +++ b/tools/firmware/hvmloader/pci.c
>>>> @@ -33,6 +33,13 @@ uint32_t pci_mem_start = HVM_BELOW_4G_MM
>>>>  const uint32_t pci_mem_end = RESERVED_MEMBASE;
>>>>  uint64_t pci_hi_mem_start = 0, pci_hi_mem_end = 0;
>>>>  
>>>> +/*
>>>> + * BARs larger than this value are put in 64-bit space unconditionally.  
>>>> That
>>>> + * is, such BARs also don't play into the determination of how big the 
>>>> lowmem
>>>> + * MMIO hole needs to be.
>>>> + */
>>>> +#define HUGE_BAR_THRESH GB(1)
>>>
>>> I would be fine with defining this to an even lower number, like
>>> 256Mb, as to avoid as much as possible memory relocation in order to
>>> make the MMIO hole bigger.
>>
>> As suggested in a post-commit-message remark, the main question then is
>> how to justify this.
> 
> I think the justification is to avoid having to relocate memory in
> order to attempt to make the hole below 4Gb larger.

Upon further thinking about it, I'm now pretty convinced that any lowering
of the boundary would better be a separate change. Right here I'd like to
stick to just the technically implied boundary.

>>>> @@ -446,8 +455,9 @@ void pci_setup(void)
>>>>           *   the code here assumes it to be.)
>>>>           * Should either of those two conditions change, this code will 
>>>> break.
>>>>           */
>>>> -        using_64bar = bars[i].is_64bar && bar64_relocate
>>>> -            && (mmio_total > (mem_resource.max - mem_resource.base));
>>>> +        using_64bar = bars[i].is_64bar && bar64_relocate &&
>>>> +            (mmio_total > (mem_resource.max - mem_resource.base) ||
>>>> +             bar_sz > HUGE_BAR_THRESH);
>>>>          bar_data = pci_readl(devfn, bar_reg);
>>>>  
>>>>          if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
>>>> @@ -467,7 +477,8 @@ void pci_setup(void)
>>>>                  resource = &mem_resource;
>>>>                  bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
>>>>              }
>>>> -            mmio_total -= bar_sz;
>>>> +            if ( bar_sz <= HUGE_BAR_THRESH )
>>>> +                mmio_total -= bar_sz;
>>>
>>> I'm missing the part where hvmloader notifies QEMU of the possibly
>>> expanded base and size memory PCI MMIO regions, so that those are
>>> reflected in the PCI root complex registers?
>>
>> I don't understand this comment: I'm not changing the interaction
>> with qemu at all. Whatever the new calculation it'll be communicated
>> to qemu just as before.
> 
> That wasn't a complain about the patch, just me failing to see where
> this is done.

I see. Is there any such needed though? There's nothing root-complex-ish
in PIIX4 after all, for not knowing of PCIe yet. The only datasheet I
have readily available is for a slightly older variant of the 82371AB,
yet I can't spot any registers there which would need updating (to
inform qemu).

>>> Overall I think we could simplify the code by having a hardcoded 1Gb
>>> PCI MMIO hole below 4Gb, fill it with all the 32bit BARs and
>>> (re)locate all 64bit BARs above 4Gb (not that I'm requesting you to do
>>> it here).
>>
>> I'm afraid that would not work very well with OSes which aren't 64-bit
>> BAR / PA aware (first and foremost non-PAE 32-bit ones). Iirc that's
>> the reason why it wasn't done like you suggest back at the time.
> 
> There will still be a ~1Gb window < 4Gb, so quite a bit of space.

Yet not enough to fit a single 1Gb BAR.

> I'm unsure whether such OSes will have drivers to manage devices with
> that huge BARs in the first place.

Assuming at least basic functionality of gfx cards is backwards
compatible, I see nothing wrong with an old driver successfully attaching
to a modern card surfacing, say, a 256Mb BAR.

I'm afraid we need to be conservative here and keep configurations working
which in principle can work without using any 64-bit addresses.

Jan



 


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