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Re: [PATCH] x86/IO-APIC: Improve APIC_TMR accesses
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 24 Jul 2024 12:10:47 +0200
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 24 Jul 2024 10:10:54 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 24.07.2024 12:08, Andrew Cooper wrote:
> On 24/07/2024 8:56 am, Jan Beulich wrote:
>> On 23.07.2024 22:37, Andrew Cooper wrote:
>>> XenServer's instance of coverity complains of OVERFLOW_BEFORE_WIDEN in
>>> mask_and_ack_level_ioapic_irq(), which is ultimately because of v being
>>> unsigned long, and (1U << ...) being 32 bits.
>> Which of course is bogus when the shift amount is masked down to 5 bits.
>> May I ask that you express this somehow in the wording.
>
> How about this?
>
> Coverity's reasoning isn't correct. (1U << (x & 0x1f)) can't ever
> overflow, but the complaint is really based on having to expand the
> RHS. While this can be fixed by changing v to be unsigned int, take the
> opportunity to better still.
Reads good, thanks.
Jan
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