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Re: [PATCH] x86/cpufeatures: Add new cpuid features in SPR to featureset
- To: Matthew Barnes <matthew.barnes@xxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 15 Aug 2024 18:06:56 +0200
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Thu, 15 Aug 2024 16:07:08 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 14.08.2024 17:52, Matthew Barnes wrote:
> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -121,6 +121,7 @@ XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode
> Extensions */
> XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */
> XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */
> XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD
> Extensions-3 */
> +XEN_CPUFEATURE(SDGB, 1*32+11) /* Silicon Debugging */
There looks to be a typo here - SDBG is what the SDM says. I also think the
comment might better mention the MSR this controls (IA32_DEBUG_INTERFACE),
as "Silocon Debugging" may mean a lot of different things.
Jan
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