Re: [PATCH v2] x86/cpufeatures: Add new cpuid features in SPR to featureset

[Jan Beulich <jbeulich@xxxxxxxx>]

On 21.08.2024 17:34, Matthew Barnes wrote:
> Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids
> within Dom0, there exist unrecognised features.
> 
> This patch adds these features as macros to the CPU featureset,
> disabled by default.
> 
> Signed-off-by: Matthew Barnes <matthew.barnes@xxxxxxxxx>

I don't strictly mind the patch in this shape, but ...

> @@ -276,10 +283,13 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* 
> MSR_TSX_FORCE_ABORT.RTM_ABORT */
>  XEN_CPUFEATURE(SERIALIZE,     9*32+14) /*A  SERIALIZE insn */
>  XEN_CPUFEATURE(HYBRID,        9*32+15) /*   Heterogeneous platform */
>  XEN_CPUFEATURE(TSXLDTRK,      9*32+16) /*a  TSX load tracking suspend/resume 
> insns */
> +XEN_CPUFEATURE(PCONFIG,       9*32+18) /*   PCONFIG insn */
>  XEN_CPUFEATURE(ARCH_LBR,      9*32+19) /*   Architectural Last Branch Record 
> */
>  XEN_CPUFEATURE(CET_IBT,       9*32+20) /*   CET - Indirect Branch Tracking */
> +XEN_CPUFEATURE(AMX_BF16,      9*32+22) /*   Tile computational operations on 
> bfloat16 numbers */
>  XEN_CPUFEATURE(AVX512_FP16,   9*32+23) /*A  AVX512 FP16 instructions */
>  XEN_CPUFEATURE(AMX_TILE,      9*32+24) /*   AMX Tile architecture */
> +XEN_CPUFEATURE(AMX_INT8,      9*32+25) /*   Tile computational operations on 
> 8-bit integers */
>  XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
> Intel) */
>  XEN_CPUFEATURE(STIBP,         9*32+27) /*A  STIBP */
>  XEN_CPUFEATURE(L1D_FLUSH,     9*32+28) /*S  MSR_FLUSH_CMD and L1D flush. */

... having had a respective (more complete) patch pending for years I really
wonder if it shouldn't be that one to be taken. While it would need adjustment
to go ahead of other stuff (as posted in v3), I don't think it has any true
dependency on earlier patches in the AMX series. IOW I could re-post v4
standalone, and then we'd have a more complete view on AMX as well as proper
dependencies in place.

Thoughts?

Jan