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Re: [PATCH v2] x86/cpufeatures: Add new cpuid features in SPR to featureset


  • To: Alejandro Vallejo <alejandro.vallejo@xxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Mon, 2 Sep 2024 10:53:39 +0200
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  • Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx, Matthew Barnes <matthew.barnes@xxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Delivery-date: Mon, 02 Sep 2024 08:53:49 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 02.09.2024 10:46, Alejandro Vallejo wrote:
> On Wed Aug 21, 2024 at 5:07 PM BST, Jan Beulich wrote:
>> On 21.08.2024 17:34, Matthew Barnes wrote:
>>> Upon running `xen-cpuid -v` on a host machine with Sapphire Rapids
>>> within Dom0, there exist unrecognised features.
>>>
>>> This patch adds these features as macros to the CPU featureset,
>>> disabled by default.
>>>
>>> Signed-off-by: Matthew Barnes <matthew.barnes@xxxxxxxxx>
>>
>> I don't strictly mind the patch in this shape, but ...
>>
>>> @@ -276,10 +283,13 @@ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* 
>>> MSR_TSX_FORCE_ABORT.RTM_ABORT */
>>>  XEN_CPUFEATURE(SERIALIZE,     9*32+14) /*A  SERIALIZE insn */
>>>  XEN_CPUFEATURE(HYBRID,        9*32+15) /*   Heterogeneous platform */
>>>  XEN_CPUFEATURE(TSXLDTRK,      9*32+16) /*a  TSX load tracking 
>>> suspend/resume insns */
>>> +XEN_CPUFEATURE(PCONFIG,       9*32+18) /*   PCONFIG insn */
>>>  XEN_CPUFEATURE(ARCH_LBR,      9*32+19) /*   Architectural Last Branch 
>>> Record */
>>>  XEN_CPUFEATURE(CET_IBT,       9*32+20) /*   CET - Indirect Branch Tracking 
>>> */
>>> +XEN_CPUFEATURE(AMX_BF16,      9*32+22) /*   Tile computational operations 
>>> on bfloat16 numbers */
>>>  XEN_CPUFEATURE(AVX512_FP16,   9*32+23) /*A  AVX512 FP16 instructions */
>>>  XEN_CPUFEATURE(AMX_TILE,      9*32+24) /*   AMX Tile architecture */
>>> +XEN_CPUFEATURE(AMX_INT8,      9*32+25) /*   Tile computational operations 
>>> on 8-bit integers */
>>>  XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
>>> Intel) */
>>>  XEN_CPUFEATURE(STIBP,         9*32+27) /*A  STIBP */
>>>  XEN_CPUFEATURE(L1D_FLUSH,     9*32+28) /*S  MSR_FLUSH_CMD and L1D flush. */
>>
>> ... having had a respective (more complete) patch pending for years I really
>> wonder if it shouldn't be that one to be taken. While it would need 
>> adjustment
>> to go ahead of other stuff (as posted in v3), I don't think it has any true
>> dependency on earlier patches in the AMX series. IOW I could re-post v4
>> standalone, and then we'd have a more complete view on AMX as well as proper
>> dependencies in place.
>>
>> Thoughts?
>>
>> Jan
> 
> Oh! I had no idea you already posted patches to enable AMX. Is this the one?
> 
> https://lore.kernel.org/xen-devel/322de6db-e01f-0b57-5777-5d94a13c441a@xxxxxxxx/

Yes. And specifically patch 9 there for the purposes here, suitably re-based
of course and extended to cover AMX-FP16 and AMX-COMPLEX.

Jan



 


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