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Re: [PATCH v1 3/4] xen/arm: mpu: Create boot-time MPU protection regions
- To: Julien Grall <julien@xxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Mon, 9 Sep 2024 08:48:43 +0000
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- Cc: Ayan Kumar Halder <ayankuma@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Mon, 09 Sep 2024 08:49:18 +0000
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- Thread-topic: [PATCH v1 3/4] xen/arm: mpu: Create boot-time MPU protection regions
Hi Julien, Ayan,
>>>
>>>> + msr PRBAR_EL2, \prbar
>>>> + msr PRLAR_EL2, \prlar
>>>> + dsb sy
>> This should be visible to outer shareable domain atleast. The reason being
>> one can use the SH[1:0] bits in PRBAR_EL2 to set the region to outer
>> shareable.
>> Thus, the writes to these registers should be visible to outer shareable
>> domain as well.
>
> I am a bit confused. SH[1:0] is about how the region will be accessed not up
> to where should registers are visible. I was expecting that the MPU registers
> only need to be visible to the MPU itself.
>
> For instance, when using the MMU, the translation unit is in the
> non-shareable domain. So a 'nsh' is sufficient regardless of the shareability
> of the page/block.
>
> This is explicitely written in the Arm Arm (see D5-4929 in ARM DDI 0487H.a)
> but I can't find a similar section for the MPU yet. Although, I would be a
> bit surprised if the MPU is not in the non-shareable domain... Maybe this
> could be clarified with Arm?
I got the feedback that DSB SY is ok here
>
> Anyway, for now, I am open to use 'dsb sy' with a TODO to revisit it.
>
>>>> + isb
>
> Re-quoting the spec from you previous answer:
>
> ```
> Writes to MPU registers are only guaranteed to be visible
> following a Context synchronization event and DSB operation.
> ```
>
> So this suggests that it should be first an 'isb' and then a 'dsb'. Any
> reason you wrote it the other way around?
I chased this internally and it was suggested the current order, dsb followed
by the isb: DSB ensures the completion of prior
instructions before the next executes, and then ISB ensures subsequent
instruction fetch observes the updated MPU state.
Probably I will raise something to make awareness around the misleading order
of that phrase.
Cheers,
Luca
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