Re: [PATCH v6 6/9] xen/riscv: introduce functionality to work with CPU info

[Jan Beulich <jbeulich@xxxxxxxx>]

On 12.09.2024 11:27, oleksii.kurochko@xxxxxxxxx wrote:
> As I mentioned above, interrupts will be disabled until tp is set.

Okay, so all good then

> Even
> if they aren’t disabled, tp will be set to 0 because, at the moment the
> secondary CPU boots, CSR_SSCRATCH will be 0, which indicates that the
> interrupt is from Xen.
> 
>> - like you do - transiently setting tp to CPU0's value (and hence >
> risking corruption of its state).
> I think I’m missing something—why would the secondary CPU have the same
> value as CPU0? If we don’t set up the tp register when the secondary
> CPU boots, it will contain a default value, which is expected upon
> boot. It will retain this value until setup_tp() is called, which will
> then set tp to pcpu_info[SECONDARY_CPU_ID].

Just to clarify (shouldn't matter in practice according to what you
said above) - in

FUNC(setup_tp)
        la      tp, pcpu_info
        li      t0, PCPU_INFO_SIZE
        mul     t1, a0, t0
        add     tp, tp, t1
        ret
END(setup_tp)

you start with setting tp to the CPU0 value. You only then adjust tp (3
insns later) to the designated value. If you wanted to play safe, you'd
do it e.g. like this

FUNC(setup_tp)
        la      t0, pcpu_info
        li      t1, PCPU_INFO_SIZE
        mul     t1, a0, t1
        add     tp, t0, t1
        ret
END(setup_tp)

Jan