[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] arm/smmu: Complete SMR masking support
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Michal Orzel <michal.orzel@xxxxxxx>
- Date: Tue, 17 Sep 2024 09:46:50 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=citrix.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0)
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VfMjepAr20TL4fC2BXKyDs+vJ/PLOqlSGGgES8qV0Qs=; b=JlCe/4pmjkVAK5p+0n5DYLhc7dom8cSzyvgxa26/4lWCbTov0n5cPIm4K9fLF1WRotx3YCOQOWEur06qwNwBGtfR98fBniWuTUAmE1nwL0M6PMu5RlZpt9h/SMA55bzas+1+Ec810LOMvW3uZAFhsDZZOf1RvwJnEtuAHBUpFmtq0Zj+jolEXmoXqzrgS8mj2PI2C/Nvkk7qKoz/p3k50dGJicVQUtQ50OfDVVMOSXlMN6CCNzax2yaQqGrcQyy2f+f9hdEzbHOCrABcKCLQETGy6wJXci0h9Qy0KvqXIlBdjSDhh/0guU7nnMga1MLDJMt3iQLXs8NtXISn34xxYg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DJ0Vn9lqpA9mcM7x2QgcZfiH5bJic+yu5N51nts5me0j7QN8g/OdnZ0iKFDWEkPII4HXb3FoeMkYs6mXkPeE5zP41KFzQlhGf3T1lo7UHF4gawmkD3BlrlS8lpVNIXLdT1wE52GUcRPt62E+PZ+vAWhsxpGTl4XUUfZcpHmxyP9zjN73xDAtfzqvX3/qYVL59Li8s+Wha5k5/koL1qzNNlgi/NL3bSSruHWA03XEQUp8Gu7YeX5asvnNEGhrlJWKrmevo6Ma4gqGLrP7bh4d3kSu8L1H53OQXytMMz3HlqeZEhdfdh6saASCQd34MIH8B8E2x2mD3S/tl4O8pqkLOw==
- Cc: Julien Grall <julien@xxxxxxx>, Rahul Singh <rahul.singh@xxxxxxx>, "Stefano Stabellini" <sstabellini@xxxxxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Tue, 17 Sep 2024 07:47:20 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 04/09/2024 14:50, Andrew Cooper wrote:
>
>
> On 04/09/2024 1:43 pm, Michal Orzel wrote:
>> diff --git a/xen/drivers/passthrough/arm/smmu.c
>> b/xen/drivers/passthrough/arm/smmu.c
>> index f2cee82f553a..4c8a446754cc 100644
>> --- a/xen/drivers/passthrough/arm/smmu.c
>> +++ b/xen/drivers/passthrough/arm/smmu.c
>> @@ -1619,19 +1619,21 @@ static int arm_smmu_master_alloc_smes(struct device
>> *dev)
>> spin_lock(&smmu->stream_map_lock);
>> /* Figure out a viable stream map entry allocation */
>> for_each_cfg_sme(cfg, i, idx, fwspec->num_ids) {
>> + uint16_t mask = (fwspec->ids[i] >> SMR_MASK_SHIFT) &
>> SMR_MASK_MASK;
>
> Not related to the change itself, but consider using MASK_EXTR() ?
>
> It reduces code volume for the reader, and removes a class of errors by
> accidentally mismatching the mask/shift constants.
>
> In x86 in particular, we're trying to remove the SHIFT constants and
> only have the MASKs.
>
> Although it looks like this is an abnormal pair to begin with, being
> shift then mask, rather than the more usual mask then shift.
Thanks for reminding about MASK_EXTR. However this won't apply here.
SMR_MASK_MASK is defined
as 0x7FFF and used elsewhere in the code together with shift. It would need to
be defined as
0x7FFF0000 (and thus reflect the actual mask field of the register) to work
with MASK_EXTR.
~Michal
|
