Re: [PATCH] x86/shutdown: mask LVTERR ahead of offlining CPUs

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Thu, Sep 19, 2024 at 10:19:49PM +0200, Andrew Cooper wrote:
> On 19/09/2024 4:27 pm, Roger Pau Monne wrote:
> > Leaving active interrupt sources targeting APIC IDs that are offline can be
> > problematic on AMD machines during shutdown.
> 
> What exactly qualifies as "offline" here?
> 
> We don't self-INIT, so I'm guessing we leave the APIC in some kind of
> disabled state, especially given ...

I would think it's the APIC software disabling done in the SVR
register.  Otherwise it might be such disabling, plus putting the CPU
in the hlt loop with interrupts disabled.

> >   This is due to AMD local APICs
> > reporting Receive Accept Errors when a message is not handled by any APIC on
> > the system.
> 
> ... this.
> 
> 
> >   Note Intel SDM states that Receive Accept Errors are only reported
> > on P6 family and Pentium processors.
> >
> > If at shutdown an active interrupt source is left targeting an offline APIC 
> > ID,
> > the following can be seen on AMD boxes:
> >
> > Hardware Dom0 shutdown: rebooting machine
> > APIC error on CPU0: 00(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > APIC error on CPU0: 08(08), Receive accept error
> > [...]
> >
> > Thus preventing the shutdown.  In the above case the interrupt source that 
> > was
> > left targeting an offline APIC ID was the serial console one
> 
> While masking LVTERR might allow more progress, it's not a wise approach.
> 
> The real issue here is that the UART driver is still active as we're
> trying to tear the system down.  If nothing else, it's rude to leave an
> active interrupt source for the kexec kernel to deal with.

While we could attempt to shutdown interrupts on the clean
shutdown/reboot paths, do we want to attempt doing the same on the
crash path?

There's an increased risk of further fallout and inability to jump
into the crash kernel as more logic is added to the hand-over path.

> IMO, we should shut the UART down like other devices, and move it back
> into polled mode.

Yeah, dealing with the UART should be doable, but we have no guarantee
that dom0 will have unmapped all interrupts it owns before shutdown,
much less when crashing.  So we could attempt to mitigate, but it's
possibly a non-trivial amount of logic to be added.

> > , so printing of
> > the local APIC ESR lead to more unhandled messages on the APIC bus, leaving 
> > the
> > host unable to make progress.
> 
> Minor note, but there's not been an APIC bus in decades.  Here, I'd
> simply say "lead to more console IRQs, and more errors".

I think some of the manuals that I have still mention the "APIC bus".

> >
> > Mask LVTERR ahead of bringing any CPU offline, thus avoiding receiving
> > interrupts for any APIC reported errors.  Note that other local APIC errors
> > will also be ignored.  At the point where the masking is done it's unlikely 
> > for
> > any reported APIC errors to be meaningful anyway, the system is about to 
> > reboot
> > or power off.
> >
> > The LVTERR masking could be limited to AMD, but there's no guarantee that in
> > the future Intel parts also start reporting the error, thus hitting the same
> > issue.  Unifying behavior across vendors when possible seems more desirable.
> > The local APIC gets wholesale disabled as part of offlining the CPUs and
> > bringing the system down in __stop_this_cpu().
> >
> > Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
> > ---
> > Note a similar issue possibly exists in the nmi_shootdown_cpus() path, 
> > however
> > that being a crash path it is more complicated to uniformly mask the LVTERR
> > strictly ahead of offlining CPUs.  That path is also more resilient AFAICT, 
> > as
> > nmi_shootdown_cpus() disables interrupts at the start (so no LVTERR 
> > interrupt
> > will be handled) and the CPUs are stopped using an NMI, which would bypass 
> > any
> > LVTERR processing.
> > ---
> >  xen/arch/x86/smp.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/xen/arch/x86/smp.c b/xen/arch/x86/smp.c
> > index 04c6a0572319..399ec7491ac6 100644
> > --- a/xen/arch/x86/smp.c
> > +++ b/xen/arch/x86/smp.c
> > @@ -348,6 +348,11 @@ static void cf_check stop_this_cpu(void *dummy)
> >          halt();
> >  }
> >  
> > +static void cf_check mask_lvterr(void *dummy)
> > +{
> > +    apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
> > +}
> > +
> >  /*
> >   * Stop all CPUs and turn off local APICs and the IO-APIC, so other OSs 
> > see a 
> >   * clean IRQ state.
> > @@ -364,6 +369,18 @@ void smp_send_stop(void)
> >          fixup_irqs(cpumask_of(cpu), 0);
> >          local_irq_enable();
> >  
> > +        /*
> > +         * Mask the local APIC error vector ahead of stopping CPUs.
> > +         *
> > +         * On AMD the local APIC will report Receive Accept Errors if the
> > +         * destination APIC ID of an interrupt message is not online.  
> > There's
> > +         * no guarantee that fixup_irqs() will evacuate all interrupts -
> > +         * possibly because the sole CPU remaining online doesn't have 
> > enough
> > +         * vectors to accommodate all.
> > +         */
> > +        smp_call_function(mask_lvterr, NULL, true);
> > +        mask_lvterr(NULL);
> > +
> >          smp_call_function(stop_this_cpu, NULL, 0);
> 
> Irrespective of the question over approach, stop_this_cpu() should end
> up clearing LVTERR.  Why doesn't that suffice?

No, because those are no ordered.  The sequence needs to strictly be:

 - Mask LVTERR on all CPUs.
 <wait for masking to be done uniformly>
 - Stop CPUs.

Otherwise CPUs might be stopped before LVTERR has been uniformly
masked, leading to Receive accept error reported on the CPUs that
don't yet have LVTERR masked.

Thanks, Roger.