[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v3 5/6] xen/arm: mpu: Enable MPU
On 22/10/2024 10:56, Luca Fancellu wrote: On 22 Oct 2024, at 10:47, Julien Grall <julien@xxxxxxx> wrote: Hi Luca, On 22/10/2024 10:41, Luca Fancellu wrote:On 21 Oct 2024, at 17:27, Julien Grall <julien@xxxxxxx> wrote:2) dsb+isb barrier after enabling the MPU, since we are enabling the MPU but also because we are disabling the background regionTBH, I don't understand this one. Why would disabling the background region requires a dsb + isb? Do you have any pointer in the Armv8-R specification?I’m afraid this is only my deduction, Section C1.4 of the Arm® Architecture Reference Manual Supplement Armv8, for R-profile AArch64 architecture, (DDI 0600B.a) explains what is the background region, it says it implements physical address range(s), so when we disable it, we would like any data access to complete before changing this implementation defined range with the ranges defined by us tweaking PRBAR/PRLAR, am I right? My mental model for the ordering is similar to a TLB flush which is: 1/ dsb nsh 2/ tlbi 3/ dsb nsh 4/ isbEnabling the MPU is effectively 2. AFAIK, 1 is only necessary to ensure the update to the page-tables. But it is not a requirement to ensure any data access are completed (otherwise, we would have needed a dsb sy because we don't know how far the access are going...). Cheers, -- Julien Grall
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