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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH 30/36] xen/8250-uart: add missing definitions
From: Denis Mukhin <dmukhin@xxxxxxxx> Added missing definitions needed for NS8250 UART emulator. Signed-off-by: Denis Mukhin <dmukhin@xxxxxxxx> --- xen/include/xen/8250-uart.h | 82 +++++++++++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 21 deletions(-) diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h index d13352940c13c50bac17d4cdf2f3bf584380776a..51c9b8c5fc3b8d9fa4b93f7722acb963fdf52a3d 100644 --- a/xen/include/xen/8250-uart.h +++ b/xen/include/xen/8250-uart.h @@ -32,16 +32,22 @@ #define UART_MCR 0x04 /* Modem control */ #define UART_LSR 0x05 /* line status */ #define UART_MSR 0x06 /* Modem status */ +#define UART_SCR 0x07 /* Scratch pad */ #define UART_USR 0x1f /* Status register (DW) */ #define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */ #define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */ #define UART_XR_EFR 0x09 /* Enhanced function register (Exar) */ +/* ns8250 emulator: range of emulated registers [0..UART_MAX-1] */ +#define UART_MAX (UART_SCR + 1) + /* Interrupt Enable Register */ #define UART_IER_ERDAI 0x01 /* rx data recv'd */ #define UART_IER_ETHREI 0x02 /* tx reg. empty */ #define UART_IER_ELSI 0x04 /* rx line status */ #define UART_IER_EMSI 0x08 /* MODEM status */ +#define UART_IER_MASK \ + (UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI | UART_IER_EMSI) /* Interrupt Identification Register */ #define UART_IIR_NOINT 0x01 /* no interrupt pending */ @@ -51,12 +57,21 @@ #define UART_IIR_THR 0x02 /* - tx reg. empty */ #define UART_IIR_MSI 0x00 /* - MODEM status */ #define UART_IIR_BSY 0x07 /* - busy detect (DW) */ +#define UART_IIR_FE0 BIT(6, U) /* FIFO enable #0 */ +#define UART_IIR_FE1 BIT(7, U) /* FIFO enable #1 */ +#define UART_IIR_FE_MASK (UART_IIR_FE0 | UART_IIR_FE1) /* FIFO Control Register */ -#define UART_FCR_ENABLE 0x01 /* enable FIFO */ -#define UART_FCR_CLRX 0x02 /* clear Rx FIFO */ -#define UART_FCR_CLTX 0x04 /* clear Tx FIFO */ -#define UART_FCR_DMA 0x10 /* enter DMA mode */ +#define UART_FCR_ENABLE BIT(0, U) /* enable FIFO */ +#define UART_FCR_CLRX BIT(1, U) /* clear Rx FIFO */ +#define UART_FCR_CLTX BIT(2, U) /* clear Tx FIFO */ +#define UART_FCR_DMA BIT(3, U) /* enter DMA mode */ +#define UART_FCR_RESERVED0 BIT(4, U) /* reserved; always 0 */ +#define UART_FCR_RESERVED1 BIT(5, U) /* reserved; always 0 */ +#define UART_FCR_RTB0 BIT(6, U) /* receiver trigger bit #0 */ +#define UART_FCR_RTB1 BIT(7, U) /* receiver trigger bit #1 */ +#define UART_FCR_TRG_MASK (UART_FCR_RTB0 | UART_FCR_RTB1) + #define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */ #define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */ #define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */ @@ -64,17 +79,17 @@ /* * Note: The FIFO trigger levels are chip specific: - * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 - * PC16550D: 1 4 8 14 xx xx xx xx - * TI16C550A: 1 4 8 14 xx xx xx xx - * TI16C550C: 1 4 8 14 xx xx xx xx - * ST16C550: 1 4 8 14 xx xx xx xx - * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 - * NS16C552: 1 4 8 14 xx xx xx xx - * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 - * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 - * TI16C752: 8 16 56 60 8 16 32 56 - * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 + * PC16550D: 1 4 8 14 xx xx xx xx + * TI16C550A: 1 4 8 14 xx xx xx xx + * TI16C550C: 1 4 8 14 xx xx xx xx + * ST16C550: 1 4 8 14 xx xx xx xx + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 + * NS16C552: 1 4 8 14 xx xx xx xx + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 + * TI16C752: 8 16 56 60 8 16 32 56 + * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA */ #define UART_FCR_R_TRIG_00 0x00 #define UART_FCR_R_TRIG_01 0x40 @@ -96,11 +111,32 @@ #define UART_LCR_CONF_MODE_B 0xBF /* Configuration mode B */ /* Modem Control Register */ -#define UART_MCR_DTR 0x01 /* Data Terminal Ready */ -#define UART_MCR_RTS 0x02 /* Request to Send */ -#define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_DTR BIT(0, U) /* Data Terminal Ready */ +#define UART_MCR_RTS BIT(1, U) /* Request to Send */ +#define UART_MCR_OUT1 BIT(2, U) /* OUT1: interrupt mask */ +#define UART_MCR_OUT2 BIT(3, U) /* OUT2: interrupt mask */ +#define UART_MCR_LOOP BIT(4, U) /* Enable loopback test mode */ +#define UART_MCR_RESERVED0 BIT(5, U) /* Reserved #0 */ +#define UART_MCR_RESERVED1 BIT(6, U) /* Reserved #1 */ +#define UART_MCR_TCRTLR BIT(6, U) /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_RESERVED2 BIT(7, U) /* Reserved #2 */ +#define UART_MCR_MASK \ + (UART_MCR_DTR | UART_MCR_RTS | \ + UART_MCR_OUT1 | UART_MCR_OUT2 | \ + UART_MCR_LOOP) + +/* Modem Status Register */ +#define UART_MSR_DCTS BIT(0, U) /* Change in CTS */ +#define UART_MSR_DDSR BIT(1, U) /* Change in DSR */ +#define UART_MSR_TERI BIT(2, U) /* Change in RI */ +#define UART_MSR_DDCD BIT(3, U) /* Change in CTS */ +#define UART_MSR_CTS BIT(4, U) +#define UART_MSR_DSR BIT(5, U) +#define UART_MSR_RI BIT(6, U) +#define UART_MSR_DCD BIT(7, U) +#define UART_MSR_SHIFT 4 +#define UART_MSR_DELTA \ + (UART_MSR_DCTS | UART_MSR_DDSR | UART_MSR_TERI | UART_MSR_DDCD) /* Line Status Register */ #define UART_LSR_DR 0x01 /* Data ready */ @@ -111,6 +147,7 @@ #define UART_LSR_THRE 0x20 /* Xmit hold reg empty */ #define UART_LSR_TEMT 0x40 /* Xmitter empty */ #define UART_LSR_ERR 0x80 /* Error */ +#define UART_LSR_MASK (UART_LSR_OE | UART_LSR_BI) /* These parity settings can be ORed directly into the LCR. */ #define UART_PARITY_NONE (0<<3) @@ -119,7 +156,10 @@ #define UART_PARITY_MARK (5<<3) #define UART_PARITY_SPACE (7<<3) -/* Frequency of external clock source. This definition assumes PC platform. */ +/* + * Frequency of external UART clock source. + * Same as IBM PC master input clock frequency. + */ #define UART_CLOCK_HZ 1843200 /* Bits in Exar specific UART_XR_EFR register */ -- 2.34.1
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