[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH v1 09/11] xen/x86: implement EPP support for the AMD processors
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: "Penny, Zheng" <penny.zheng@xxxxxxx>
- Date: Sun, 26 Jan 2025 06:18:20 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SMI2dI7n/rB8+PxcfxXFwCj59zzPoInHpIQu34CHdYE=; b=ZoEaPClvcCNrq5r0UOrWmNqRV+wyz26jazXydkc5QDu1xvuaY37GrI3lV6NQrW+iME322sxTqG8MFEuYQsaQzoMhjM+/v/KhDMwACD5n7KkAvL7i9xtupXLDPCDLtCR7AYQs1genAMRB36dmlH3Ok4ogdXWxHsuTK4j3EWcooNPXsq6imze+MIqlUdr2lXQe/DRTCc+UxWjyuViXSCGoIB7YuloIAYNiFplx97pIZXkKibkBc9uJufFcXAqMDRf0Kjg5eED7ld7zqlVtOaJ/1Sli9zb0YvRBTwkWIYtzK32yZKwlPDD/0HzqqnPVcI1WU0EJS1KY1rHtiEyRfnZ5ZA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Ai9BI/dq70dYxwXnRpnoJLz1t4alxFlhi/8kOU/pCTuXeT1DJeK7QyLA+E82O8YVJ+OaYFvVBpCodg3RyQOVkrHBPWE9b6TXh/Yc/MnPb9dWFtgBJ8VAPKyzhQ7CVvtmWmaUUmMlXmo/yg2E5GzTp/LjU3aLUktkzso+bI82trNCjljzfnOckc2+3PzjnNx/P6rWxkp9CwwJ5xXZ1/9JT/Jn6SChyNlfS+x4ntGguSm1VnRKbnYOfjn/Hhl3XRbD6L83Jsw1opjB3Wud3q1FZZ/PfnhV92UAFsGa+H7qjQLMkLoVNy30bXEhRtDpn/CNCbicOFluE/ybZKnjSumynQ==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
- Cc: "Stabellini, Stefano" <stefano.stabellini@xxxxxxx>, "Huang, Ray" <Ray.Huang@xxxxxxx>, "Ragiadakou, Xenia" <Xenia.Ragiadakou@xxxxxxx>, "Andryuk, Jason" <Jason.Andryuk@xxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Sun, 26 Jan 2025 06:18:44 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Msip_labels: MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_ActionId=764e3bf6-b76a-4c11-81d9-b0c72bde7b73;MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_ContentBits=0;MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_Enabled=true;MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_Method=Standard;MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_Name=AMD Internal Distribution Only;MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_SetDate=2025-01-26T05:47:59Z;MSIP_Label_dce362fe-1558-4fb5-9f64-8a6240d76441_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d;
- Thread-index: AQHbRVznRa/Bwz7xKUirr7NfworPsbMOizuAgBpVwcA=
- Thread-topic: [PATCH v1 09/11] xen/x86: implement EPP support for the AMD processors
[AMD Official Use Only - AMD Internal Distribution Only]
Hi,
> -----Original Message-----
> From: Jan Beulich <jbeulich@xxxxxxxx>
> Sent: Thursday, January 9, 2025 7:38 PM
> To: Penny, Zheng <penny.zheng@xxxxxxx>
> Cc: Stabellini, Stefano <stefano.stabellini@xxxxxxx>; Huang, Ray
> <Ray.Huang@xxxxxxx>; Ragiadakou, Xenia <Xenia.Ragiadakou@xxxxxxx>;
> Andryuk, Jason <Jason.Andryuk@xxxxxxx>; Andrew Cooper
> <andrew.cooper3@xxxxxxxxxx>; Roger Pau Monné <roger.pau@xxxxxxxxxx>; Julien
> Grall <julien@xxxxxxx>; Stefano Stabellini <sstabellini@xxxxxxxxxx>; xen-
> devel@xxxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH v1 09/11] xen/x86: implement EPP support for the AMD
> processors
>
> On 03.12.2024 09:11, Penny Zheng wrote:
> > +
> > + /* Initial min/max values for CPPC Performance Controls Register */
> > + max_perf = data->hw.highest_perf;
> > + min_perf = data->hw.lowest_perf;
> > +
> > + if ( data->policy == CPUFREQ_POLICY_PERFORMANCE )
> > + min_perf = max_perf;
>
> Why can't this be done ...
>
> > + /* CPPC EPP feature require to set zero to the desire perf bit */
> > + des_perf = 0;
> > +
> > + if ( data->policy == CPUFREQ_POLICY_PERFORMANCE )
> > + /* Force the epp value to be zero for performance policy */
> > + epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE;
>
> ... here as well? And why is there nothing respective for ...
Ack
>
> > + else if ( data->policy == CPUFREQ_POLICY_POWERSAVE )
> > + /* Force the epp value to be 0xff for powersave policy */
> > + epp = CPPC_ENERGY_PERF_MAX_POWERSAVE;
>
> ... this case (e.g. setting max_perf from min_perf)?
If we put max_perf = min_perf = lowest_perf/lowest_nonlinear_perf, then
we are putting core in idle state. That's how we offline the cpu core in Linux
amd pstate epp driver, see
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/cpufreq/amd-pstate.c?h=v6.13#n1643
>
> Jan
Many thanks,
Penny
|
