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Re: [PATCH v3 19/24] xen/8250-uart: add missing definitions


  • To: Denis Mukhin <dmkhn@xxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Wed, 29 Jan 2025 08:56:03 +0100
  • Autocrypt: addr=jbeulich@xxxxxxxx; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL
  • Cc: dmukhin@xxxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxxx, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Jason Andryuk <jason.andryuk@xxxxxxx>
  • Delivery-date: Wed, 29 Jan 2025 07:56:08 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 29.01.2025 02:16, Denis Mukhin wrote:
> On Tuesday, January 28th, 2025 at 2:34 PM, Jason Andryuk 
> <jason.andryuk@xxxxxxx> wrote:
> 
>>
>>
>> On 2025-01-03 20:58, Denis Mukhin via B4 Relay wrote:
>>
>>> From: Denis Mukhin dmukhin@xxxxxxxx
>>>
>>> Added missing definitions needed for NS8250 UART emulator.
>>>
>>> Re-used newly introduced MSR definitions in the existing ns16550 driver.
>>>
>>> Also, fixed indentation in a comment for FCR register.
>>>
>>> Signed-off-by: Denis Mukhin dmukhin@xxxxxxxx
>>> ---
>>> xen/drivers/char/ns16550.c | 6 ++--
>>> xen/include/xen/8250-uart.h | 78 
>>> +++++++++++++++++++++++++++++++++------------
>>> 2 files changed, 60 insertions(+), 24 deletions(-)
>>
>>> diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
>>> index 
>>> d13352940c13c50bac17d4cdf2f3bf584380776a..6d1af31d582a3dd674a401d7f649e28c889cdc3e
>>>  100644
>>> --- a/xen/include/xen/8250-uart.h
>>> +++ b/xen/include/xen/8250-uart.h
>>
>>> @@ -51,12 +54,19 @@
>>> #define UART_IIR_THR 0x02 /* - tx reg. empty /
>>> #define UART_IIR_MSI 0x00 / - MODEM status /
>>> #define UART_IIR_BSY 0x07 / - busy detect (DW) /
>>> +#define UART_IIR_FE 0xC0 / FIFO enabled (2 bits) */
>>>
>>> /* FIFO Control Register /
>>> -#define UART_FCR_ENABLE 0x01 / enable FIFO /
>>> -#define UART_FCR_CLRX 0x02 / clear Rx FIFO /
>>> -#define UART_FCR_CLTX 0x04 / clear Tx FIFO /
>>> -#define UART_FCR_DMA 0x10 / enter DMA mode */
>>
>>
>> 0x10 is bit 4...
>>
>>> +#define UART_FCR_ENABLE BIT(0, U) /* enable FIFO /
>>> +#define UART_FCR_CLRX BIT(1, U) / clear Rx FIFO /
>>> +#define UART_FCR_CLTX BIT(2, U) / clear Tx FIFO /
>>> +#define UART_FCR_DMA BIT(3, U) / enter DMA mode */
>>
>>
>> Now it's 0x08. Is this a bug fix? Looks like UART_FCR_DMA is unused.
> 
> Correct, NS16550 defines FCR DMA as bit#3 (0x08):
>   https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> 
>   Table 7-3. Summary of Accessible Registers
>   7.7.2 FIFO Control Register (FCR)

Any actual corrections you make need mentioning in the description.
I'm glad Jason spotted this; I did overlook it.

Jan



 


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