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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v1] xen/arm: AArch32-V8R: Add MPU register definitions
Add the definitions for HPRBAR<0..31>, HPRLAR<0..31> and HPRENR.
The definitions are taken from ARM DDI 0568A.c ID110520, E2.2.3 HPRBAR<n>,
E2.2.4 HPRENR and E2.2.6 HPRLAR<n>.
Introduce pr_t typedef which is a structure having the prbar and prlar members,
each being structured as the registers of the AArch32-V8R architecture.
This is the arm32 equivalent of
"arm/mpu: Introduce MPU memory region map structure".
Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
---
This patch should be applied after
"[PATCH v3 0/7] First chunk for Arm R82 and MPU support" in order to enable
compilation for AArch32.
xen/arch/arm/include/asm/arm32/mpu.h | 59 +++++++++++
xen/arch/arm/include/asm/mpu.h | 4 +
xen/arch/arm/include/asm/mpu/cpregs.h | 135 ++++++++++++++++++++++++++
3 files changed, 198 insertions(+)
create mode 100644 xen/arch/arm/include/asm/arm32/mpu.h
diff --git a/xen/arch/arm/include/asm/arm32/mpu.h
b/xen/arch/arm/include/asm/arm32/mpu.h
new file mode 100644
index 0000000000..4aabd93479
--- /dev/null
+++ b/xen/arch/arm/include/asm/arm32/mpu.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * mpu.h: Arm Memory Protection Unit definitions for aarch64.
+ */
+
+#ifndef __ARM_ARM32_MPU_H
+#define __ARM_ARM32_MPU_H
+
+#define XN_EL2_ENABLED 0x1
+
+#ifndef __ASSEMBLY__
+
+/* Hypervisor Protection Region Base Address Register */
+typedef union {
+ struct {
+ unsigned int xn:1; /* Execute-Never */
+ unsigned int ap:2; /* Acess Permission */
+ unsigned int sh:2; /* Sharebility */
+ unsigned int res0:1; /* Reserved as 0 */
+ unsigned int base:26; /* Base Address */
+ } reg;
+ uint32_t bits;
+} prbar_t;
+
+/* Hypervisor Protection Region Limit Address Register */
+typedef union {
+ struct {
+ unsigned int en:1; /* Region enable */
+ unsigned int ai:3; /* Memory Attribute Index */
+ /*
+ * There is no actual ns bit in hardware. It is used here for
+ * compatibility with Armr64 code. Thus, we are reusing a res0 bit for
ns.
+ */
+ unsigned int ns:1; /* Reserved 0 by hardware */
+ unsigned int res0:1; /* Reserved 0 by hardware */
+ unsigned int limit:26; /* Limit Address */
+ } reg;
+ uint32_t bits;
+} prlar_t;
+
+/* Protection Region */
+typedef struct {
+ prbar_t prbar;
+ prlar_t prlar;
+ uint64_t p2m_type; /* Used to store p2m types. */
+} pr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARM_ARM32_MPU_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h
index 77d0566f97..67127149c0 100644
--- a/xen/arch/arm/include/asm/mpu.h
+++ b/xen/arch/arm/include/asm/mpu.h
@@ -8,8 +8,12 @@
#if defined(CONFIG_ARM_64)
# include <asm/arm64/mpu.h>
+#elif defined(CONFIG_ARM_32)
+# include <asm/arm32/mpu.h>
#endif
+#define PRENR_MASK GENMASK(31, 0)
+
#define MPU_REGION_SHIFT 6
#define MPU_REGION_ALIGN (_AC(1, UL) << MPU_REGION_SHIFT)
#define MPU_REGION_MASK (~(MPU_REGION_ALIGN - 1))
diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h
b/xen/arch/arm/include/asm/mpu/cpregs.h
index d5cd0e04d5..7cf52aa09a 100644
--- a/xen/arch/arm/include/asm/mpu/cpregs.h
+++ b/xen/arch/arm/include/asm/mpu/cpregs.h
@@ -6,18 +6,153 @@
/* CP15 CR0: MPU Type Register */
#define HMPUIR p15,4,c0,c0,4
+/* CP15 CR6: Protection Region Enable Register */
+#define HPRENR p15,4,c6,c1,1
+
/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */
#define HPRSELR p15,4,c6,c2,1
#define HPRBAR p15,4,c6,c3,0
#define HPRLAR p15,4,c6,c8,1
+/* CP15 CR6: MPU Protection Region Base/Limit Address Register */
+#define HPRBAR0 p15,4,c6,c8,0
+#define HPRLAR0 p15,4,c6,c8,1
+#define HPRBAR1 p15,4,c6,c8,4
+#define HPRLAR1 p15,4,c6,c8,5
+#define HPRBAR2 p15,4,c6,c9,0
+#define HPRLAR2 p15,4,c6,c9,1
+#define HPRBAR3 p15,4,c6,c9,4
+#define HPRLAR3 p15,4,c6,c9,5
+#define HPRBAR4 p15,4,c6,c10,0
+#define HPRLAR4 p15,4,c6,c10,1
+#define HPRBAR5 p15,4,c6,c10,4
+#define HPRLAR5 p15,4,c6,c10,5
+#define HPRBAR6 p15,4,c6,c11,0
+#define HPRLAR6 p15,4,c6,c11,1
+#define HPRBAR7 p15,4,c6,c11,4
+#define HPRLAR7 p15,4,c6,c11,5
+#define HPRBAR8 p15,4,c6,c12,0
+#define HPRLAR8 p15,4,c6,c12,1
+#define HPRBAR9 p15,4,c6,c12,4
+#define HPRLAR9 p15,4,c6,c12,5
+#define HPRBAR10 p15,4,c6,c13,0
+#define HPRLAR10 p15,4,c6,c13,1
+#define HPRBAR11 p15,4,c6,c13,4
+#define HPRLAR11 p15,4,c6,c13,5
+#define HPRBAR12 p15,4,c6,c14,0
+#define HPRLAR12 p15,4,c6,c14,1
+#define HPRBAR13 p15,4,c6,c14,4
+#define HPRLAR13 p15,4,c6,c14,5
+#define HPRBAR14 p15,4,c6,c15,0
+#define HPRLAR14 p15,4,c6,c15,1
+#define HPRBAR15 p15,4,c6,c15,4
+#define HPRLAR15 p15,4,c6,c15,5
+#define HPRBAR16 p15,5,c6,c8,0
+#define HPRLAR16 p15,5,c6,c8,1
+#define HPRBAR17 p15,5,c6,c8,4
+#define HPRLAR17 p15,5,c6,c8,5
+#define HPRBAR18 p15,5,c6,c9,0
+#define HPRLAR18 p15,5,c6,c9,1
+#define HPRBAR19 p15,5,c6,c9,4
+#define HPRLAR19 p15,5,c6,c9,5
+#define HPRBAR20 p15,5,c6,c10,0
+#define HPRLAR20 p15,5,c6,c10,1
+#define HPRBAR21 p15,5,c6,c10,4
+#define HPRLAR21 p15,5,c6,c10,5
+#define HPRBAR22 p15,5,c6,c11,0
+#define HPRLAR22 p15,5,c6,c11,1
+#define HPRBAR23 p15,5,c6,c11,4
+#define HPRLAR23 p15,5,c6,c11,5
+#define HPRBAR24 p15,5,c6,c12,0
+#define HPRLAR24 p15,5,c6,c12,1
+#define HPRBAR25 p15,5,c6,c12,4
+#define HPRLAR25 p15,5,c6,c12,5
+#define HPRBAR26 p15,5,c6,c13,0
+#define HPRLAR26 p15,5,c6,c13,1
+#define HPRBAR27 p15,5,c6,c13,4
+#define HPRLAR27 p15,5,c6,c13,5
+#define HPRBAR28 p15,5,c6,c14,0
+#define HPRLAR28 p15,5,c6,c14,1
+#define HPRBAR29 p15,5,c6,c14,4
+#define HPRLAR29 p15,5,c6,c14,5
+#define HPRBAR30 p15,5,c6,c15,0
+#define HPRLAR30 p15,5,c6,c15,1
+#define HPRBAR31 p15,5,c6,c15,4
+#define HPRLAR31 p15,5,c6,c15,5
+
/* Aliases of AArch64 names for use in common code */
#ifdef CONFIG_ARM_32
/* Alphabetically... */
#define MPUIR_EL2 HMPUIR
#define PRBAR_EL2 HPRBAR
+#define PRBAR0_EL2 HPRBAR0
+#define PRBAR1_EL2 HPRBAR1
+#define PRBAR2_EL2 HPRBAR2
+#define PRBAR3_EL2 HPRBAR3
+#define PRBAR4_EL2 HPRBAR4
+#define PRBAR5_EL2 HPRBAR5
+#define PRBAR6_EL2 HPRBAR6
+#define PRBAR7_EL2 HPRBAR7
+#define PRBAR8_EL2 HPRBAR8
+#define PRBAR9_EL2 HPRBAR9
+#define PRBAR10_EL2 HPRBAR10
+#define PRBAR11_EL2 HPRBAR11
+#define PRBAR12_EL2 HPRBAR12
+#define PRBAR13_EL2 HPRBAR13
+#define PRBAR14_EL2 HPRBAR14
+#define PRBAR15_EL2 HPRBAR15
+#define PRBAR16_EL2 HPRBAR16
+#define PRBAR17_EL2 HPRBAR17
+#define PRBAR18_EL2 HPRBAR18
+#define PRBAR19_EL2 HPRBAR19
+#define PRBAR20_EL2 HPRBAR20
+#define PRBAR21_EL2 HPRBAR21
+#define PRBAR22_EL2 HPRBAR22
+#define PRBAR23_EL2 HPRBAR23
+#define PRBAR24_EL2 HPRBAR24
+#define PRBAR25_EL2 HPRBAR25
+#define PRBAR26_EL2 HPRBAR26
+#define PRBAR27_EL2 HPRBAR27
+#define PRBAR28_EL2 HPRBAR28
+#define PRBAR29_EL2 HPRBAR29
+#define PRBAR30_EL2 HPRBAR30
+#define PRBAR31_EL2 HPRBAR31
+#define PRENR_EL2 HPRENR
#define PRLAR_EL2 HPRLAR
+#define PRLAR0_EL2 HPRLAR0
+#define PRLAR1_EL2 HPRLAR1
+#define PRLAR2_EL2 HPRLAR2
+#define PRLAR3_EL2 HPRLAR3
+#define PRLAR4_EL2 HPRLAR4
+#define PRLAR5_EL2 HPRLAR5
+#define PRLAR6_EL2 HPRLAR6
+#define PRLAR7_EL2 HPRLAR7
+#define PRLAR8_EL2 HPRLAR8
+#define PRLAR9_EL2 HPRLAR9
+#define PRLAR10_EL2 HPRLAR10
+#define PRLAR11_EL2 HPRLAR11
+#define PRLAR12_EL2 HPRLAR12
+#define PRLAR13_EL2 HPRLAR13
+#define PRLAR14_EL2 HPRLAR14
+#define PRLAR15_EL2 HPRLAR15
+#define PRLAR16_EL2 HPRLAR16
+#define PRLAR17_EL2 HPRLAR17
+#define PRLAR18_EL2 HPRLAR18
+#define PRLAR19_EL2 HPRLAR19
+#define PRLAR20_EL2 HPRLAR20
+#define PRLAR21_EL2 HPRLAR21
+#define PRLAR22_EL2 HPRLAR22
+#define PRLAR23_EL2 HPRLAR23
+#define PRLAR24_EL2 HPRLAR24
+#define PRLAR25_EL2 HPRLAR25
+#define PRLAR26_EL2 HPRLAR26
+#define PRLAR27_EL2 HPRLAR27
+#define PRLAR28_EL2 HPRLAR28
+#define PRLAR29_EL2 HPRLAR29
+#define PRLAR30_EL2 HPRLAR30
+#define PRLAR31_EL2 HPRLAR31
#define PRSELR_EL2 HPRSELR
+
#endif /* CONFIG_ARM_32 */
#endif /* __ARM_MPU_CPREGS_H */
--
2.25.1
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